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I want to design to pipeline adc, for training.

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totoro

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Could you give me a reasonable specification which need include speed, resolution, power at least.
I prefer to choose vdd as 3.3v, 0.35 or 0.25 CMOS process.
The followering purposes are expected to achieve though this training:
1. deeply understanding the S/H circuit design
2. high speed comparator design technique
3. digital calibrate technique

Any one would help me?
 

You can refer some of the datasheets of ppipelined ADC for the specification..
For training, I guess, 10bit - 50M to 100MHz is ok..
 

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    totoro

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go to **broken link removed** to download some thesis and the follow them.....

Good Luck
 

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    totoro

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The book "Data onverters for communication" is also a good reference.
 

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    totoro

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Check this for understanding and practicing:

**broken link removed**


It is a very good Application Notes.
 

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    totoro

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