nickb1
Newbie level 4
Hello,
I am trying to interface with the ADC on my Spartan 3E starter board.
First I made a 1.5Mhz clock so the sample rate will be above 40kHz (i want to sample audio).
Then I made a state machine that, in the first state (set_amp), sets the preamp with a gain of -1.
Te next state is the idle state which sets de AD_CONV high for two clock periods so the ADC can take a sample.
The last state (read_adc) reads out the two channels in 34 cycles. I use a seperate state machine to turn the serial clock of during the AD_CONV time.
But it doesnt seem to work, the output (as I can see on the leds) is switching very fast between 0 and the maximum input, also when I connect the input to the 1.8V supply nothing happens.
Hope someone can point me in the right direction.
Many thanks!
I am trying to interface with the ADC on my Spartan 3E starter board.
First I made a 1.5Mhz clock so the sample rate will be above 40kHz (i want to sample audio).
Then I made a state machine that, in the first state (set_amp), sets the preamp with a gain of -1.
Te next state is the idle state which sets de AD_CONV high for two clock periods so the ADC can take a sample.
The last state (read_adc) reads out the two channels in 34 cycles. I use a seperate state machine to turn the serial clock of during the AD_CONV time.
But it doesnt seem to work, the output (as I can see on the leds) is switching very fast between 0 and the maximum input, also when I connect the input to the 1.8V supply nothing happens.
Hope someone can point me in the right direction.
Many thanks!
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AD is
Port ( SPI_SCK : out STD_LOGIC;
AD_CONV : out STD_LOGIC;
SPI_MISO : in STD_LOGIC;
SPI_MOSI : out STD_LOGIC;
AMP_CS : out STD_LOGIC;
AMP_SHDN : out STD_LOGIC;
AMP_DOUT : in STD_LOGIC;
mclk: in STD_LOGIC;
amplitude1: out STD_LOGIC_VECTOR(13 downto 0);
amplitude2: out STD_LOGIC_VECTOR(13 downto 0);
LED : out std_logic_vector(7 downto 0));
end AD;
architecture Behavioral of AD is
type state_type is (idle, set_amp, read_adc);
signal state : state_type := set_amp;
type state_type_clock is (clock_on, clock_off);
signal state_clock : state_type_clock := clock_off;
signal cnt : integer range 0 to 40 := 0;
signal clk_sample : STD_LOGIC;
signal gain_set : STD_LOGIC := '0';
signal amplitude1_buffer : STD_LOGIC_VECTOR(13 downto 0);
signal amplitude2_buffer : STD_LOGIC_VECTOR(13 downto 0);
signal gain1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
signal gain2 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
begin
-- 1.5MHz clock
clock_divider : process (mclk)
variable counter : integer range 0 to 33000001;
begin
if(rising_edge(mclk)) then
if counter = 33 then
clk_sample <= not clk_sample;
counter := 0;
else
counter := counter + 1;
end if;
end if;
end process;
sclk_clock : process(mclk)
begin
if(rising_edge(mclk)) then
case state_clock is
when clock_on =>
SPI_SCK <= clk_sample;
when clock_off =>
SPI_SCK <= '0';
end case;
LED(0) <= amplitude1_buffer(5);
LED(1) <= amplitude1_buffer(6);
LED(2) <= amplitude1_buffer(7);
LED(3) <= amplitude1_buffer(8);
LED(4) <= amplitude1_buffer(9);
LED(5) <= amplitude1_buffer(10);
LED(6) <= amplitude1_buffer(11);
LED(7) <= amplitude1_buffer(12);
end if;
end process;
main : process (clk_sample)
begin
if(rising_edge(clk_sample)) then
-- Set gain at -1
case state is
when set_amp =>
AMP_CS <= '0';
AMP_SHDN <= '0';
if (cnt < 4) then
SPI_MOSI <= gain2(3 - cnt);
cnt <= cnt + 1;
state <= set_amp;
state_clock <= clock_on;
elsif (cnt > 3 and cnt < 8) then
SPI_MOSI <= gain1(7 - cnt);
cnt <= cnt + 1;
state <= set_amp;
elsif (cnt = 8) then
cnt <= 0;
AMP_CS <= '1';
state <= idle;
end if;
when idle =>
-- 13ns delay
if (cnt < 2) then
AD_CONV <= '1';
cnt <= cnt + 1;
state <= idle;
elsif (cnt = 2) then
AD_CONV <= '0';
cnt <= 0;
state <= read_adc;
end if;
when read_adc =>
state_clock <= clock_on;
if (cnt < 2) then
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 1 and cnt < 16) then
amplitude1_buffer(15 - cnt) <= SPI_MISO;
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 15 and cnt < 18) then
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 17 and cnt < 32) then
amplitude2_buffer(31 - cnt) <= SPI_MISO;
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 31 and cnt < 34) then
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt = 34) then
cnt <= 0;
amplitude1<=amplitude1_buffer;
amplitude2<=amplitude2_buffer;
state_clock <= clock_off;
state <= idle;
end if;
end case;
end if;
end process;
end Behavioral;
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