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well biasing and threshold voltage effects

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a_shirwaikar

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hey,
could anyone please help me out with two things??

i have read in various documents that well biasing is not feasible below 65nm. However, I haven't managed to find any papers that prove these claims.

also, i know that threshold voltage affects both timing and leakage. but could you please give me formulae related to this?? derivations would be ideal.

Could anyone give me some explanations and also direct me to some papers on the above two mentioned topics?? thanks for any help, i really appreciate it :lol:
 

it can, definitely. but its redundant. because channel leakage no longer plays a dominant role, its the thin gate oxides and short channel effects which come into play.
but i want a paper on some sort of analysis done on the same
 
Short channel effect can be reduced with bigger length in analog circuit.
There is some gate leakage compensation circuit too.
Increase well bias can also achieve meaningful effect as expected.
 

can well biasing reduce gate leakage in any way?
 

No, gate leakage is decided by gate oxide thickness and its quality.
However, it can be compensated.
 

a_shirwaikar said:
can well biasing reduce gate leakage in any way?
Click to expand...

According to this article, Ig can be somewhat lessened by optimizing region of operation and area of your devices. Vth has an impact as well (hence well biasing) but I am not sure how large nor if it is in the right direction...
 

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