divide a number in vhdl

Below this text there's a code and I have a problem. I'm trying tod divide a number per 10, because I want to make the table of the numbers just from "0" to "9" but the compilator its saying that I cannot use the operator "/"...and I don't know why...Thanks guys

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity LUT1 is
port(
clk: in std_logic;
led: out bit_vector(6 downto 0);
entrada: in std_logic_vector(5 downto 0));
end LUT1;

Architecture table of LUT1 is

constant max: integer := 50000000;--This are just for the first process
constant half: integer := max/2;--This are just for the first process
signal newclk: std_logic;--This are just for the first process
signal count: integer range 0 to max;--This are just for the first process

shared variable bcd: std_logic_vector (2 downto 0):="000";--This are just for the second process
shared variable aux: integer;--This are just for the second process
constant deu: std_logic_vector(5 downto 0):="001010";--constant to divide per 10 in binary


begin

divide: process--This process its only to divide the main clock of the main board.

begin
wait until clk'event and
clk='1';
if
count<max then count<=count + 1;
else count <= 0;
end if;

if count < half then newclk<='0';
else newclk <='1';

end if;

end process divide;

conv: process (newclk)--This process works like we shown you the last time, it's showing the number that you are entering by the switches but this time we just want to divide the number from the switches per 10 and then show the number.
begin


bcd := entrada / deu;-- Here we have the problem, we cannot divide this variable per 10, you know why? The compilator says that this operator "/" is not valid

case bcd is
when "0000000000000000" => LED <= "1000000";--0
when "0000000000000001" => LED <= "1111001";--1
when "0000000000000010" => LED <= "0100100";--2
when "0000000000000011" => LED <= "0110000";--3
when "0000000000000100" => LED <= "0011001";--4
when "0000000000000101" => LED <= "0010010";--5
when "0000000000000110" => LED <= "0000010";--6
when "0000000000000111" => LED <= "1111000";--7
when "0000000000001000" => LED <= "0000000";--8
when "0000000000001001" => LED <= "0010000";--9
when "0000000000001010" => LED <= "1000000";--10
when "0000000000001011" => LED <= "1111001";--11
when "0000000000001100" => LED <= "0100100";--12

--- ...until 100

when others => LED <= "1000000";
end case;
end process conv;
end table;

is "/"(a,b) defined for unsigned values? I'm guessing it isn't. Further, you would need synthesis support for inferred division, as well as shared variables.

you mean that maybe I have to transform "entrada" and "deu" to unsigned variable? and also I need more variables to do the division?

Can you write in vhdl what are you suggesting?

No, the division is not support as such in any synthesis tool.
Divide by 2, 4, 8, ... will work as this synthesizes to a shift right.

A division by 10 will need to be implemented with an other algorithm. I can refer to 'non-restoring division algorithm'.

Do you actually need to divide by 10 or 100?

Maybe this if .. then ... else can bring solution

in pseudo code:
if < 10
digit10 = 0
digit = number
else if < 20
digit10 = 1
digit = number - 10
else if < 30
digit10 = 2
digit = number - 20
and so on ...

you can use / if you use the numeric_std package. but then its not recomended because divide requires several pipeline stages, that you can't get with a divide function. you will need to use a divide ip block, which is usually provided by your vendor.

If I convert "entrada" to Integer then divide it by 10 and then convert it back to std_logic??? because sounds stupid that this device cannot divide per 10...

you can do that, but its still not recomended. it won't work very fast. divides that are not a bit shift are slow

The problem is here

Click to expand...

The problem is not there. It has been explained in detail, that std_logic_arith respectively std_logic_unsigned don't recognize the divison operator. ieee.numeric_std in contrast does. In addition, the synthesis tool must be able to "infer" divider IP, which is mostly the case. With the old synopsys libraries, division is however suppported for integer, so there is a possible workaround.

FvM said:

The problem is not there. It has been explained in detail, that std_logic_arith respectively std_logic_unsigned don't recognize the divison operator. ieee.numeric_std in contrast does. In addition, the synthesis tool must be able to "infer" divider IP, which is mostly the case. With the old synopsys libraries, division is however suppported for integer, so there is a possible workaround.

Click to expand...

Its also one of the problem... u cant assign 5-bit signal to 3-bit signal. and its obvious you should use numeric_std.

I agree with FvM about the libraries support.

Thanks guys for your help! now its working