Rocketmagnet
Junior Member level 3
Hi all,
I am writing my first Verilog program, but I'm finding it quite hard. I just don't understand why it doesn't do what I expect.
Can anyone critique this for me, many thanks. I would really like to get to know Verilog better, so I can write my own peripherals for the Cypress PSoC.
The program should do this (See attached image too):
* If two rising edges are seen on the input (EDGES) within 15 clock cycles the output (CS) goes low.
* If a falling edge is seen on the input, CS goes high.
This is the code I have written so far:
I am writing my first Verilog program, but I'm finding it quite hard. I just don't understand why it doesn't do what I expect.
Can anyone critique this for me, many thanks. I would really like to get to know Verilog better, so I can write my own peripherals for the Cypress PSoC.
The program should do this (See attached image too):
* If two rising edges are seen on the input (EDGES) within 15 clock cycles the output (CS) goes low.
* If a falling edge is seen on the input, CS goes high.
This is the code I have written so far:
Code:
module CS_Detect (
Counter,
CS,
E,
CLK,
EDGES
);
output [3:0] Counter; // Used to time the edges
output CS; // The main output
output E; // A debugging output
// gives a pulse on rising edge of EDGES
input CLK;
input EDGES;
reg T;
reg E;
reg CS;
reg Counter;
always @(EDGES or T)
begin
E <= EDGES & !T;
end
always @(posedge CLK)
begin
if (EDGES & !T) begin // CS Rising
if (Counter > 0) begin // OMFG, the counter HASN'T timed out. This is the second rising edge!
CS = 0;
end else begin // Counter has timed out. This is a possible first edge
Counter = 15;
end
end
if (!EDGES & T) begin // CS Falling
CS = 1;
end
if (Counter > 0) Counter = Counter - 1;
end
always @(negedge CLK)
begin
T = EDGES;
end
endmodule