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but in very small technology i.e. 65nm the it is very difficult to make the DAC by using the charge sharing. So can any one suggest some solution of this problem.
What is the resolution of your DAC?
For IC DACs, a "current steering" topology might be helpful because you dont have cappacitors neither resistors to integrate (which consume large area) but the chip becomes larger for 12 or more bits and also the decoding circuitry becomes more complex.
The basic idea is to steer a current into a current source by biassing or not a pair of two NMOS transistors (complementary biassed).
I can provide you some basic circuitry if you are interested in this topology.
What is the resolution of your DAC?
For IC DACs, a "current steering" topology might be helpful because you dont have cappacitors neither resistors to integrate (which consume large area) but the chip becomes larger for 12 or more bits and also the decoding circuitry becomes more complex.
The basic idea is to steer a current into a current source by biassing or not a pair of two NMOS transistors (complementary biassed).
I can provide you some basic circuitry if you are interested in this topology.
but iam getting the outputimpedence at 100MHz -15dB it is too low value.If i decrease the transistor sizes then region of transistors are in linear region.
anybody suggest the transistor sizes for improving the outputimpedence and also the transistors are in saturation region.
---------- Post added at 13:41 ---------- Previous post was at 13:22 ----------
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