Event Control contains a complex event expression?

Using Altera Quartus I get the warning:

"Event Control contains a complex event expression", for the following code:

always@(negedge signal1 && address==4'b0001 && chip_sel==0)

Is it bad practice to have an always@ occur for more than one signal or is this just a reminder for the programmer?

Possibly you want to use:

The handling of the actual values of address and chip_sel is to be done inside the main block of this always. Not in the sensitivity list (which is what you're trying to do now).

Try this:

Ah ok Thanks. Yes i was thinking to try that code. My original code works, but not as robust or good practice as what you have suggested.

I'm only occasionally using Verilog, but I don't think that the or combination of edge and level sensitive events is synthesizable. I must admit, that I didn't find a similar construct anywhere, except for the IEEE Verilog spec.
And anyway, it won't turn the original "bad practice" in something good, I fear.

The original construct, if I understand it right, is evaluating a logic expression and then uses it as a clock. Because the logic expression is very likely having glitches, it will rarely work.

Using asynchronous action instead (level sensitive expressions) may work in special cases but is also far from good coding.

Why not using simple, straightforward synchronous coding, that does all register assignments under a clock edge?

if u want to use edge and level sensitive in a same block,maybe you can use a edge detect circuit to detect edge sensitive signal,then you can turn it to level sensitive.

i think it is not good to use the combination combination of edge and level sensitive events .just for discussion

FvM, Verilog started with "or" as the seperator for the sensitivity list. The VHDL "," was added in Verilog-2001. But Verilog is different than VHDL in that the edge events themselves are used in the sensitivity list. VHDL simply places "Clk" in the list and then qualifies the code in the block with "if rising_edge(Clk) then". VHDL, in theory, evaluates (and skips) the content of each process on every negative clock edge. Verilog is written to explicitly say "don't even attempt to evaluate this on the negative clock edge". Of course it is likely that every decent simulator would have realized this during the "optimization" phase.

The code above probably synthesizes to a combinatorial circuit -- similar to including a clock in a VHDL process but forgetting to add the "if rising_edge(Clk)" line.

IIRC, verilog as a language allows signals to not be globally static to a much higher degree than VHDL. eg, connecting A&&B to a port in verilog is valid. Placing A^B in a sensitivity list might make some sense.

Both languages are moving away from requiring sensitivity list management, so it'll will eventually be a non-issue. I've never seen anyone use both pos/negedge events and non-edge events in the same sensitivity list, nor anyone use operation other than the list seperators " or " or "," in the sensitivity list.

I'm not sure there is a valid way to write the original code. the OP seems to have found a way that works.