ASIC DC Synthesis Warning

Here is the flow which we are using :

We are using memories in our design. We have generated memories using Memory compiler and then converted .lib files to .db using readlib & writelib commands.

Memory compiler generates following four files for Memory files:

1. Memory_gen_ff_1.1_-40.0_syn.lib
2. Memory_gen_ff_1.1_125.0_syn.lib
3. Memory_gen_tt_1.0_25.0_syn.lib
4. Memory_gen_ss_0.9_125.0_syn.lib

Further to generate the .db files we are using "Memory_gen_ff_1.1_-40.0_syn.lib".

We are using fast.db for our ASIC. When we are running integrated top (with memory .db files), we are getting warning as below,

##
Warning: The trip points for the library named USERLIB differ from those in the library named fast. (TIM-164) ##

Looks we are missing something in flow while generating/integrating memory files with our RTL.

It's just a tripping point of memory and std lib is different.
man page will give you more details on the warning.

Depending on the condition used during characterization, libraries are sometimes defined with different trip points.
Old libraries are often using 10%-90% as trip points with a derate of 1, meaning that the timing values given are for a 10-90% ramp. Recent libraries often use 30%-70%, with a derate of 0.5. It means the timing is given for 30-70%, but extrapolated (the derate part).
Check the value of your libraries to be sure there is no problem. If you have 10%-90%, derate=1 and 30%-70%, derate=0.5 there should be no problem at timing analysis (in that case you can discard the warning). If it's different, you need to check the compatibility for timing analysis.