stitching via size vs other vias ?

I'm working on a design that uses a 19.7mil/0.5mm drill via for most signals and a 28mil/0.7mm drill via for higher current lines.

I'd like to add some stitching vias to various ground/power planes and am curious what an appropriate via size would be for those. I want to use something smaller than 0.5mm in order to fit them into smallish areas.

Does that make sense or should I just use the smaller of the two existing vias for this purpose?

thanks

In my designs I use the smallest finished hole size the fab house is comfortable with, usually a 0.25mm, and have them tented over. I say finished hole size because I'm not sure and don't care what drill they actually use.

Now if you are expecting some high currents through those via you might want to use fewer larger vias just so the hole count doesn't get way out of hand.

Ray

How you configure stitching vias depends on what you want to achieve.

1. If adding vias is itended for increased current capacity then you can use a larger diameter drill and fewer vias. In this case, I would always calculate exactly how many vias I will need to carry current. An easy way to know this is to use pi to calculate circumference of via drill then use this circumference in any trace width calculator to find out how much current each via can carry and how much of a temperature rise I want to allow. (usually within the barrel of a via plating will be about 1 ounce)
2. If adding vias is itended for shielding than I might approach this a bit differently. For shielding, I typically want to use a smaller via diameter but use more of them to create something of a forest effect offsetting each row by 50%. If I am shielding a Tr line I will usually space vias at 1mm along Tr line and 2mm for each row therafter.

Regards,
Eda

In this particular situation I am trying to adhere to the layout guidelines provided in the datasheets for parts like the LT3480, which shows 18+ gnd vias as a thermal conduction path to the gnd plane. I believe the main goal is to establish as low inductance as possible in the return path and provide good thermal conductivity.

Thanks for the tips - I might have to stick around this board and learn an extra thing or two...

Those vias are primarily thermal; you can get the current in with top layer copper but you might not be able to get the heat away. I wrote up a note on how to do thermal vias in footprints in Altium, but even if you use another EDA package you might want to check out the links mentioned. (https://www.edaboard.com/threads/205944/#post868451)

General recommendations are to keep the vias 0.3mm or smaller, tent them with a dot of soldermask 0.1mm larger than the hole on the top side to prevent wicking, and pattern the solder paste in a checkerboard of around 60-70% coverage. You should also check with LTC to see if they have more detailed recommendations for that part.

If you have a ground plane, the thermal vias will provide a path to help get the heat away. If not, put as much copper as possible on the bottom layer and that will help dissipate heat. If heat is a problem and the PCB is mounted close to a metal enclosure, you might be able to put a thermal pad (i.e. 3M or Laird) between the bottom copper area and the enclosure to sink heat away.

decibel08 said:

Thanks for the tips - I might have to stick around this board and learn an extra thing or two...

Click to expand...

I've been an engineer for 40 years and have worked on most everything under the sun and indeed there is a thing or two to learn here. I read posts here that often serve to humble me by showing me much I don't know.

Ray

Try an get the IPC-7093 specification, it covers the design assembly and manufacturing issues regarding bottom terminated components and thermal vias.