[SOLVED] what is clock latency and clock uncertainty

clock uncertainty

what is clock latency and clock uncertainty plz tell me

clock latency

Clock latency is defined as the amount of time from the clock origin point to the sync pin of the flop

and uncertainity is jitter which is generated by the oscillator that is PLL

set clock uncertainty

Clock latency is the delay between the clock source and the clock pin. It is dependant on hardware, PCB, traces, etc.

Clock uncertainty is the difference between 2 clock signals. It could be the same clock signal arriving at two different points on a PCB. (Skew).

Hope this helps.

Red

what is clock uncertainty

clock uncertainty is the skew , so we should do CTS to fix them. clock latency is the delay from the souce to the clock pin ,we should do STA to make the timing ok!

what is clock latency

Clock Latency is the delay in the clock signal from the clock source port to any clock pin in the circuit. Clock uncertainity is jitter. But jitter and skew are two different terms. Jitter is the variation in the clock period ( that is the clock edge might not be at
the required time). Jitter coud be caused due to various on chip variations.Jitter need not be expressed with respect to two nodes. Clock Skew is the difference between the clock arrival times at two different nodes.

clock uncertainity

Let me try to clear up some of the confusing terminology - clear terminology allows for clear thinking.

The first important point is that there are two phases in the design of a clock signal. At first the clock is in "ideal mode" (e.g.: during RTL design, during synthesis and during placement). An "ideal" clock has no physical distribution tree, it just shows up magically on time at all the clock pins.
The second phase comes when clock tree synthesis (CTS) inserts an actual tree of buffers into the design that carries the clock signal from the clock source pin to the (thousands) of flip-flops that need to get it. CTS is done after placement and before routing. After CTS is finished, the clock is said to be in "propagated mode".

Now we can get to your questions:

What is clock latency? Clock latency is an ideal mode term. It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin. This is a delay specified by the user - not a real, measured thing. (In fact there is 'clock source latency' and 'clock network latency' - the difference is not important for this discussion). When the clock is actually created, then that same delay is now referred to as the "insertion delay". Insertion delay (ID) is a real, measurable delay path through a tree of buffers. Sometimes the clock latency is interpreted as a desired target value for the insertion delay.

What is clock uncertainty? In ideal mode the clock signal can arrive at all clock pins simultaneously. But in fact, that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty. For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.
A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:
(a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
(b) The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.
(c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

clock latency

Thank you MarcS for your explanation

clock uncertainty latency

Clock jitter could also be defined as the crosstalk effect on the clock nets. Since a clock tree is used, different clock branches can have different crosstalk and therefore different jitter. Therefore this effect needs to be modeled or uncertainty introduced to add enough margin.

How is the clock jitter handled in the design? Do we need to add extra uncertainty to fix it, or is it handled by an increased on chip variation setting?

clock uncertainty and clock jitter both are same?

The clock uncertainty contains two parts: skew and jitter.

clock source latency

Hey MarcS thanx ... great explanation

set clock latency

binglingxiao said:

The clock uncertainty contains two parts: skew and jitter.

Click to expand...

right, and for detailed information, refer to MarcS's reply. It is very detail and professional.

reasons for clock jitter clock tree

clock uncertainty: skew and jitter
clock latency:
1 source latency: clock source(oscilator) to the pin
of you chip
2 network delay: clock input pin to each FF

clock latency = source latency + network latency

Hey Marcs,

If we are taking on chip variation as a factor for the clock uncertainity then why
is there OCV margin set seperately while timing the design.????????

Thanks
Ahtesham

Re: clock uncertainty latency

malamos said:

Clock jitter could also be defined as the crosstalk effect on the clock nets. Since a clock tree is used, different clock branches can have different crosstalk and therefore different jitter. Therefore this effect needs to be modeled or uncertainty introduced to add enough margin.

How is the clock jitter handled in the design? Do we need to add extra uncertainty to fix it, or is it handled by an increased on chip variation setting?

Click to expand...

clock jitter and cross talk are entirely 2 different entities....Jitter margin is set because of PLL uncertainty...Cross talk comes because of coupling cap. between 2 nets..Dont confuse among 2

---------- Post added at 10:15 ---------- Previous post was at 10:13 ----------

hahtesham said:

Hey Marcs,

If we are taking on chip variation as a factor for the clock uncertainity then why
is there OCV margin set seperately while timing the design.????????

Thanks
Ahtesham

Click to expand...

OCV can not be predicted. You can by no chance know wat would be the temp. variation across the chip. So we set derates to account for OCV.

Re: clock uncertainity

Marcs, thanks for your great explanation.
I still have some question.
1.

MarcS said:

For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.

Click to expand...

I wonder whether it is 50 ps or 100ps. Because
creat_clock -period 1 [get_ports CLK]
set_clock_uncertainty -setup 0.1 [get_ports CLK]
Then the max allowable delay for reg2reg pah is (1-0.1-setup in lib) but not (1-0.05-setup in lib)
2.
I dont know why we need to model the clock source latency.
In my opinion, since source latency is the delay from the actual clock origin to the create_clock port but all the clock uncertainty only has relationship with the create_clock port, the considering for source latency would make no sense.

As with many in this discussion, I am having a hard time wrapping my mind around clock uncertainty. Is this just a knob that you turn up if you think you are having clock problems??? It would seem that the Design Tool (Quartus in my case) would have the best shot at adding up the delays and accounting for chip level variations. If the Altera Engineers can’t suggest and uncertainty time value, how can I?

Re: clock uncertainity

rogeret said:

Marcs, thanks for your great explanation.
I still have some question.
1.

I wonder whether it is 50 ps or 100ps. Because
creat_clock -period 1 [get_ports CLK]
set_clock_uncertainty -setup 0.1 [get_ports CLK]
Then the max allowable delay for reg2reg pah is (1-0.1-setup in lib) but not (1-0.05-setup in lib)

Click to expand...

rogeret, I guess you are right. if you do a "timing_report" in your prefered synthesis or timing analysis tool you will find the value of uncertainty and not the half of it.

Please tell me if I am wrong.

bye.

See this: https://vlsi-soc.blogspot.in/2013/04/clock-jargon-important-terms.html