writing values of a variable to a file using verilog HDL

mrflibble said:

That would be really odd.... %d should really print decimal format. Just by way of sanity check...

Code:

integer fp1;
fp1=$fopen("ctq.txt");
$fwrite(fp1,"%d\n",z);
$fwrite(fp1,"Are we sure ... %d\n", 42);
$fclose(fp1);

So do you get 42 there, or 2A?

Click to expand...

mrflibble said:

That's a different question altogether.

AFAIK the moment your precious data resides in a reg or wire, you are boned. By the time the $fwrite occurs, the tool no longer knows about it being signed or unsigned.

The "integer" datatype however is signed, and will print negative numbers using %d. So as long as your data fits in a 32-bit signed, then what you could do is take your wire/reg, typecast it into an integer, and then $fwrite that integer.

Click to expand...

dll_fpga said:

ok...fibble i got it .

but i need the numbers to be written to the file in signed format

Click to expand...

.how can this be done?
integer fp1;
fp1=$fopen("ctq.txt");
$fwrite(fp1,"%d\n",z);

using %d is giving the results in unsigned format....but i need the values to be written in signed format....

Click to expand...

module trb();
integer fp1;
integer  i=32'h FFFFFFFF;
initial	begin
 
fp1=$fopen("ctq.txt"); 
$fwrite(fp1,"Are we sure ... %d\n",i); 	

i=32'h 7FFF_FFFF;
$fwrite(fp1,"Are we sure ... %d\n",i); 

$fclose(fp1);



end 
endmodule

mrflibble said:

add something like:

Code:

integer signed_z;

...

signed_z = (z);
$fwrite(fp1,"regular z: %d\n", z);
$fwrite(fp1,"signed z: %d\n", signed_z);

But note that I tested it with 32-bits wire on purpose, that being same size operands. The integer is 32-bits as well. I have not tested it with size different from 32-bits. That's your job.

---------- Post added at 20:49 ---------- Previous post was at 20:44 ----------

Okay, now I did test it. And it does work for 32 bit. And does NOT work for 6 bit like your case, without some extra work.

So what you need to do is take your signed 6-bit "z", and extend it to a signed 32-bit version. And apply the above typecast trick.

Click to expand...

blooz said:

h**p://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf
page 4

Verilog-2001 adds two new system functions,
$signed and $unsigned. These system functions are used
to convert an unsigned value to signed
Once you declare the variable as integer .it should be signed

verify with this code just modified Mrflibbbles code to illustrate the fact
no separate format specifier is needed %d is enough if you declared variable as integer .

Code:

module trb();
integer fp1;
integer  i=32'h FFFFFFFF;
initial	begin
 
fp1=$fopen("ctq.txt"); 
$fwrite(fp1,"Are we sure ... %d\n",i); 	

i=32'h 7FFF_FFFF;
$fwrite(fp1,"Are we sure ... %d\n",i); 

$fclose(fp1);



end 
endmodule

Are we sure ... -1
Are we sure ... 2147483647


In first fwrite i is having negative sign as the MSB is 1 ,so the particular number is the 2's complement of another number (-1) .

In second one i is having Msb 0 that means a postive number.

Click to expand...