comparator input->output time limit

Hello! I am designing an comparator, with a budget of 70uA. I only care about having a clear output, and not saving that output (a latch or memory in general is not of my concern, as also hysteresis is not my concern, imagine a noise free input).

My question is the following: with such limited power, what is (in order of magnitude) my "decision time" through my circuit? I mean i've build a comparator that takes around 50nsec from the moment one input crosses the threshold of the other input till i read it to the output. I am using just some cascaded gain stages. If i use positive feedback, that delay is way more (i don't have external clock, so i use dummy resistors, and this adds unavoidably some hysteresis)....

So if i want the fastest ever comparator, how much is the delay input-->output (due to propagation delay and dynamic effects of internal caps of the transistors) that i should expect? can i get that an order of magnidude down?

Thx

PS Any ideas can be helpful, so just drop a line! thx again

Here's an example for a 3V 5ns comparator (without hysteresis), current consumption < 70µA.
0.25µm process.

if i read the graph correctly i read less than 5usec not less than 5nsec, unless i'm totally wrong.... but i'll look into the idea of the topology, thx

Understand that the speed of the comparator depends on how big your input is (i.e. the precision requirements of the comparator). More precision -> slower

For high accurate high speed comparator, both high small-signal bandwidth and high slew rate are required.

geozog86 said:

... i read less than 5usec not less than 5nsec...

Click to expand...

Oh yes, you're right, shame on me. Very sorry, indeed! :-(

For this speed, you probably need a clocked comparator. See these 2 topologies:

At 50ns and limited current budget, it will be challenging to go faster by a decade.

Comparator transition mainly comprises 2 stages.
In the saturation stage, the comparator behaves like an opamp, and so your opamp analysis skills (eg. gm, bandwidth and pole indentification) can be used to analyse the sources for delay. The input slew also plays a part in this stage.
The second stage is the slew-limiting stage. Identify the current branch in which transition is limited by slew, and assign additional current to that branch. Another thing to optimize is the load, to make sure that the output inverters are sized appropriately, and the comparator is connected to low fan-in logic. If you are really pressed for speed, you may custom design such logic based on logical effort principles.
But do bear in mind that small device sizes for increased speed also means poor offset and lower gm, hence lower resolution.

Forgot to say thanks to all of you! Great advice.