Needed tips for floorplanning memories

Hi, everybody!

Does anyone have tips for floorplanning memories?

I have a circuit with 16 blocks of memory IP, and I'm doing the floorplanning of this type of circuits for the first time. I know that the pins of the block are in one side.
I don't know what is best place to put the memories.
I attached the last layout I tested. The problem is that i needed lots of optimize steps (adding buffers or upsizing the cells) to clear all negative slacks paths. In the end this will be reflected in the power/area consumption, routing congestion, etc.

My question is:

Is it better to put all memory blocks together and put the std cells in a close area or put the memories like in the figure attached and let the std cells be placed mixed with the memories?

Thanks,

Jorge

It is actually depending on your design. Putting all memory blocks together may save area, but can cause routing congestion. The best way to figure out which way to go is to do the trial route. Just try different memory placement, and the density of fly lines can tell you the result pretty quickly.

Hi jtonfat,

I think if you place all the macros together you are bound to face congestion issues... I think what you have done in the figure should do the job..ofcourse you can play with the orientations of macros a little I feel

cheers,

I think you can go ahead with the placement...It looks good...Did you check for space to place your logic cells?