Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I fear, it's not quite clear waht your asking for. "Stuck at" normally happens, if a logic driven output never changes it's state, possibly to a logic design error, or just intentionally. If it it's not by intention, what do you want to simulate? You have to analyze the logic and find out, why the output takes the same state under all conditions.
In Verilog it is possible to set a wire to a value in test bench on the fly.
Such as you have a wire "sig" in a module called DUT
in test bench you can write
assign DUT = 1;
to cause it to one.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
