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sdf annotation simulation question

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elvishbow_zhl

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sdf annotation

HI,all

after my synthesis, there are no timing violations in the design.
Then I get sdf file and use sdf_annotate() in netlist simulation using ncverilog.

If the design has no sdf back annotation, the simulation result is correct

otherwise when I add sdf_annotate with sdf file, the result is incorrect.

What should I do the next time?

Thanks......
 

sdf simulation

Your sdf file comes from a post-layout parasitic extraction?

It isn't too strange to find some violation in final post-layout simulation: the only possible tip is to make more robust as possible your sinthesys process!

Use ever timing constraints worst than needed: so your desing will be more robust!
 

sdf annotate

In your pre-simulation, if you annotate the SDF file, the result don't meet your RTL simulation. Your can check your script file for synthesis. Maybe your design can't meet your cycle requirement.
 

sdf simulations

compare your waveforms before and after sdf annotation, pay more attention on the design inition.
maybe reset signal has some problem.
 

gate level simulation sdf

lailiya said:
compare your waveforms before and after sdf annotation, pay more attention on the design inition.
maybe reset signal has some problem.
Click to expand...

---------------------------------------------------------------------------

i agree with lailiya, sometimes the problem is from the asynchronous reset. if the timing problem happen at the very beginning of the simulation, change the reset timing, probably it will work.

--always@smart
 

netlist simulation

Before you finished your design, you need to pass the gate level simulation with the post layout sdf. Of course, PT might help you speed up the timing verification.

You might not have time for re-synthesis all your design again. You should try the in-place optimization, eco, buffer sizing, buffer insertion, ... first.
 

annotation sdf

maybe the synthesis tool and the simulation tool use different algorithm to calculate timing.So one has violation, the other doesn't
 

sdf back annotation

elvishbow_zhl said:
HI,all

after my synthesis, there are no timing violations in the design.
Then I get sdf file and use sdf_annotate() in netlist simulation using ncverilog.

If the design has no sdf back annotation, the simulation result is correct

otherwise when I add sdf_annotate with sdf file, the result is incorrect.

What should I do the next time?

Thanks......
Click to expand...

did you do STA? timing checking there is more detail

and I thought if you didn't finish layout, back annotation simulation seems not necessary.
 

gate simulations sdf

What do you mean "the result is incorrect"
Where your sdf come from??
If your sdf come from pre-sim(run DC)
then the sdf is so what you want
you need got a post-layout sdf
if it's post-layout sdf and
what you mean is Simulation Pattern check error

Just Trace the waveform
(gate level trace, recommand use Debussy)
you should be able to find timeing violations in waveform

find out why this happen , modify RTL or .....
 

.sdf simulation

Usually, the inputs (netlist & sdf file) of post-simulation is from backend layout result.

In backend layout, clock tree and scan logic will be inserted. The sdf from layout result is accurate.

If just use output from dc, as 1st synthsys is estimated (take wireload for example), many information is not correct. In this situation, even you compare dc's timing report & PT's timing report, they are also not completely match. :)
 
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