transient noise analysis

Hello all,

I have a continuous time (CT) third order delta sigma modulator that produces SNR=98dB when the circuit noise (thermal and flicker noise) is not considered in a transient simulation. When I use transient analysis with transient noise in Cadence-spectre, the SNR drops to 60dB. Replacing the circuits with VerilogA modules (noiseless modules) showed the disturbing noise is due to the Active-RC integrator. However, small signal noise analysis of the Active-RC integrator shows an input-referred noise (IRN) < -140dB/Hz, which causes the integrated in-band noise (IBN) less than -100 dB for a BW=10kHz.

When signal power is -14dB, resulting SNR should be more than 86dB, while simulation with transient noise shows SNR=60 dB.

I cannot find any other source for the noise and I wonder if the transient noise analysis is producing correct results.
Please let me know your ideas.
Thank you,
Ali

you should post the schematic and add more details.

In the transient noise set-up form, you should use: "noiseupdate=step".

Please find the enclose figures showing structure of the delta sigma modulator, test setup for the integrator, and some results for the integrator.

In the modulator only the integrator is circuit and the rest are verilog-A models.

The integrator shows input-referred noise of -147 dB, and output-referred noise less than -89dB. Please note that in a delta sigma modulator only the input-referred noise of the first integrator can reach the output of the modulator with almost no attenuation.

Transient noise analysis is set with following parameters:
noiseseed=1
noisefmax=fs (fs = 5.12MHz, the modulator bandwidth is 10 kHz)
noiseupdate=step

Adding or removing noiseupdate=step makes no difference in the final SNR of the modulator. Also noiseupdate is not available in the GUI, and I have added in the netlist manually, then ran simulation by spectre command.

The modulator can produce SNR=91.7 dB when the transient noise is disabled, which implies the modulator is operating correctly. But enabling transient noise drops the SNR to 60 dB.

Please let me know if more details are required.

Best,
Ali

Can the maximum step size in a transient simulation effect on the amount of injected noise?
fs=5.12 MHz,

tran tran stop=52m errpreset=conservative noiseseed=1 noisefmax=fs noiseupdate=step \
maxstep=1n write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5

thinking...

---------- Post added at 14:09 ---------- Previous post was at 14:02 ----------

could it be something like noise aliasing due to the clocked DAC? are you sure about the way that the input noise of every block is transferred to output?
i'll keep trying to figure out something

In a delta sigma modulator, it is well-known that only DAC and the first integrator can contribute to the output noise. It can also be tested by behavioral simulators such as Matlab and verilog-A.

I found that transient noise analysis is not match with noise analysis. An experienced designer told me that he would not rely on any of them and even consider 50% more noise. I am not sure how true this is, but may lead to over design.

Anyway, I could restore 20dB out of 30dB by better coefficient scaling in trials. Where ever the noise comes from, it can be alleviated by scaling and redistribution of the coefficients.

Ali

naderi said:

In a delta sigma modulator, it is well-known that only DAC and the first integrator can contribute to the output noise. It can also be tested by behavioral simulators such as Matlab and verilog-A.

I found that transient noise analysis is not match with noise analysis. An experienced designer told me that he would not rely on any of them and even consider 50% more noise. I am not sure how true this is, but may lead to over design.

Anyway, I could restore 20dB out of 30dB by better coefficient scaling in trials. Where ever the noise comes from, it can be alleviated by scaling and redistribution of the coefficients.

Ali

Click to expand...

i don't know with Spectre, but with ELDO the noise estimation made by NoiseTran is quite responding to the analytical calculations.

yes, i know where the noise come from, but i was wondering if aliasing phenomena due to the clocked DAC may concern.

Could you explain more on the aliasing phenomena of a clocked DAC?
My understanding is that such aliasing could occur in a clocked ADC when the input bandwidth is higher than clock frequency (fs). Then the noise distributed over the input band is folded between DC to fs/2.
In a clocked DAC, its input is digital with a bandwidth of fs/2. No extra bandwidth to alias.

Regards,
Ali

Hello naderi,

naderi said:

In a delta sigma modulator, it is well-known that only DAC and the first integrator can contribute to the output noise. It can also be tested by behavioral simulators such as Matlab and verilog-A.

I found that transient noise analysis is not match with noise analysis. An experienced designer told me that he would not rely on any of them and even consider 50% more noise. I am not sure how true this is, but may lead to over design.

Anyway, I could restore 20dB out of 30dB by better coefficient scaling in trials. Where ever the noise comes from, it can be alleviated by scaling and redistribution of the coefficients.

Ali

Click to expand...

Try with Berkeley Design Automation (BDA), Analog FastSPICE (AFS) for accurate Transient Noise analysis...
especially the kind of circuits you are working on...
BDA - AFS Transient Noise Option

Also there is a white paper from Qualcomm on ADC device noise signoff methodology at with AFS Transient Noise
http://www.berkeley-da.com/prod/datasheets/BDA_Qualcomm_ADC_Noise_WP.pdf

---manju---