Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
This is only valid for very short connections. For long connections, the metal resistance of the wire would be dominant.RC time constant is about two times bigger for one via, than for two vias.
Right, but it's not because burning off (for higher currents you need an array of vias anyway), but the minimal overlap used in submicron processes. Already a small misalignment together with some angle tilt during metal deposition may cause metal coverage failing inside the still accessible via wall. See e.g.I think the main reason is to maximize the yield....You dont want your chip to not work coz of a single via getting burnt off..