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Troubleshooting timing problems in FPGA design

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Alexium

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Greetings!
Today is the first day when my design passed physical test in FPGA. But as I repeated the same test over and over, I noticed that sometimes the design misbehaves (like 1 or 2 times out of 10). I assume it's timing problem.
So, the question is: how does one localizes and troubleshoots the timing problem? I really have no idea. Is there some procedure?
Of course, I have timing constraints. I've set them with 10 percent margin in relation to actual frequency, and they are still met.

P.S. I work with Xilinx ISE.
 

My first question would be - do you have any large amounts of asynchronous logic or latches? these cannot be controlled with normal timing constraints. If you have them, Im betting they are causing you problems.
 

Hi,

It's quite hard to debug such a problem.

Firstly, are you sure it's a timing issue ? it's may be a functional one ! because the frequency of the issues is high (10 to 20% !!)
You can check if all the asynchronous inputs are resynchronized (at least double stage), and then check that all the clock domain crossings are done properly (with FIFO or handshake or other proven techniques).

Then if you still stack, it's worth to go back to design and check the following:


Did you perform STA ? did you run some post-layout simulations in corner cases ? it's very important to perform this tasks before to move on to test on FPGA, if the STA is pass then there is a weak chance to get timing issues on target.


Yours,
 
TrickyDicky said:
My first question would be - do you have any large amounts of asynchronous logic or latches?
Click to expand...
Well, no large amounts, but I have a few. Something like one 11-bit combinatorial subtractor (outside of a clocked process) and one or two 11-bit latches.

---------- Post added at 13:53 ---------- Previous post was at 13:42 ----------
shnain said:
Firstly, are you sure it's a timing issue ? it's may be a functional one ! because the frequency of the issues is high (10 to 20% !!)
Click to expand...
Thanks for your suggestions. Yes, the frequency is high, but the amount of test runs between failures is very different from experiment to experiment, it seems to be evenly distributed. Maybe I'm getting something, but I don't see how could that be caused by a functional error.
I only have one clock domain, and I don't have asynchronous inputs. I only have RS232 module, but I've tested it quite thoroughly. I beleive I did perform STA, that's when I get the report regarding the timing constraints being met and the calculated clock period for every clock signal. But I didn't perform post-place and route simulation, thanks for suggestion.
 

TrickyDicky said:
My first question would be - do you have any large amounts of asynchronous logic or latches? these cannot be controlled with normal timing constraints. If you have them, Im betting they are causing you problems.
Click to expand...

Yes, and you have also to check if you have logic with high fanout, because the input capacitance of the loads can cause timing issues typically, such a situation should be avoided.
 
Alexium said:
Well, no large amounts, but I have a few. Something like one 11-bit combinatorial subtractor (outside of a clocked process) and one or two 11-bit latches.



latches are notorious for causing timing problems in FPGAs. Because they are asynchronous, all sorts of stuff can happen. Plus temporature becomes a factor. The setup time is probably being violated.

I recommend you remove the latches and see what happens to the problem then.
Click to expand...
 
TrickyDicky said:
latches are notorious for causing timing problems in FPGAs. Because they are asynchronous, all sorts of stuff can happen. Plus temporature becomes a factor. The setup time is probably being violated.
I recommend you remove the latches and see what happens to the problem then.
Click to expand...
I have heard latches are bad, so I try to avoid them. Unfortunately, I couldn't think of other way to solve the problem rather than use a latch. But I'll try to redesign that part and get rid of latch.
 

what are the latches used for? you mention a subtractor? why did you use it? if it was because you just HAD to get something complete in a single clock cycle, then the fundamental design is flawed.
 

I have removed the latch completely. No effect. Also, I have lowered the clock frequency from 100 to 50 MHz. No effect either.
I guess, post place and route simulation is in order...
 

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