minimum period , data pulse , minimum pulse width

Hai all. I have
1) data pulse width violations
2) minimum period violations
3) minimum pulse width violations

can any one please explain what are these violations, what are their cause and how to overcome them.

Especially data pulse width violations.

It would be grateful if any additional detailed material is provided.

Hi Jaya,

tools check for the pulse width of the clock signal in the clock network and upon reaching the flip-flop. For level-high pulse width checking, we consider maximum delay for the rising edge and minimum delay for the falling edge of the clock (and conversely for level-low pulse width checking).

When we perform pulse width check considering max and min subsequently we get worst case pulse width which is very small and violates the pulse width constraint of flop as it assumes worst-case delays for both rising and falling edges. But in reality they will be correlated i.e if the rising edge delay is min say 0.2 the falling edge delay will also be nearer to 0.2 but not at the maximum, so we use a mechanism called clock re-convergence pessimism removal to increase the accuracy of minimum pulse width checking....

cheers,

thank you for explaining.