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Taking the output from fpga

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dll_fpga

dll_fpga

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how can i view an output which is 10 bits wide and changes at 80MHZ ....the FPGA that i have has around 15 switches .... the output comes at positive edge of clock cycle but the rate is too fast to view on LEDS.......
 

Chipscope or Signal Tap II depending on which FPGA you're using is the answer.

Or you can always used dedicated logic analyzer, if availability is not a problem.
 

But chipscope cannot be accomodated in the design due to the large gate consumption....
any other alternatives?
 
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Sure! Chipscope is a viable alternative for when chipscope cannot be accomodated in the design due to the large gate consumption. Change the parameters of your design so that it does fit is what I mean. ;)

Or you could do what I did before I knew how to use chipscope.

Add a debug fifo that can capture the fast signals. Display the output of the fifo to the leds. Use switches to cycle through the fifo. Also use the switches to select display mode, so you can see the data in the fifo, the read and write word count, etc. It's a poor man's solution, but better than nothing. And if not even a small fifo is going to fit you're probably out of luck...
 
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thank you fibble.....i was thinking of using a RAM module at the output block.....is that ok?...or I will have to use FIFO instead?
 

I have absolutely no idea what you mean by that! "a ram module at the output block"? Care to make that a bit more precise? Or not. You don't have to use fifo's. It's what I used, no reason for you to use it. If you can do whatever-debugging-you-need with a "RAM module at the output block" then gogogo!

Other than that before you expend too much time and effort on workarounds.... The idea behind chipscope is that you can also use it to debug a partial design. So if your total design is so big that BigDesign + chipscope will not fit in your fpga, then for debugging only use the critical modules. As in for debugging purposes only use the critical modules + chipscope, which probably will fit in the fpga. Then when you have worked out the part that needed debugging, you can add the rest of the modules again.

Oh yeah, be sure to check out these vids on chipscope:

YouTube - How to use ChipScope Pro - (Ch 1)
YouTube - How to use ChipScope Pro - (Ch 2)
YouTube - How to use ChipScope Pro - (Ch 3)

hope that helps. :)
 

---------- Post added at 21:00 ---------- Previous post was at 21:00 ----------

[/COLOR]thanks for the suggestions.....do you have any pdf links for chipscope....?
 

hi FIbble.
my aim is not debugging ......but to take the output of my design from the FPGA.....simulation is working fine.....but since i'm getting 1 output at each posedge of clock....(clock is around 1000 mhz and i need only first 64 output values).....i was planning of writing these values to a RAM module at the output of the design.....and by changing the address(using switches) i will be able to access the ram locations that contain the output values values of my design(the output values can be seen on LED's).....?will that works?
 

Clock is around 1000 MHz? What part are you using?
 

no...i just want to convince you tht it's in MHZ range....so it's not possible to see the output directly on FPGA....i 'm using aroung 1/5th of tht....
 
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And why would not 200 MHz not be visible with a DSO or logic analyzer? But I digress. Point about frequency noted. But by talking about that "ram module", and the fact that you want a fast write clock a slow read clock, an possibly different read/write bus widths... you have just specified the perfect match for a fifo. So if I understand your design, then yeah you want a fifo there. You can put one together with a few mouse clicks in the core generator...
 

Thanks fibble....let me try to add a FIFO via coregen
 
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mrflibble said:
And why would not 200 MHz not be visible with a DSO or logic analyzer? But I digress. Point about frequency noted. But by talking about that "ram module", and the fact that you want a fast write clock a slow read clock, an possibly different read/write bus widths... you have just specified the perfect match for a fifo. So if I understand your design, then yeah you want a fifo there. You can put one together with a few mouse clicks in the core generator...
Click to expand...


hi ,
i had generated a FIFO with independent clock for read and write....now i need to see the output on LED's ,so should i use a switch to give clock for read operation?......(to give a slower clock by pressing the switches so that output is visible on led's)
or is there any other alternatives so that my output is visible on LED's .....
 
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Else you could use some counters to trigger read operation and thus get some lower frequency.Ex use some mode 16 counter If you want to do some action At every 4th clock pulse ..like wise 2^n mode to get a Nth clock pulse and reset the clock at e very nth pulse ..
 

dll_fpga said:
i had generated a FIFO with independent clock for read and write....now i need to see the output on LED's ,so should i use a switch to give clock for read operation?......(to give a slower clock by pressing the switches so that output is visible on led's)
Click to expand...

The idea is indeed to use the switches to manually generate your slow clocks etc, so you can go through the data at your leisure. Assuming that 1) you want to slowly inspect the data and 2) you really really don't have the spare resources for a simple chipscope module.
 

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