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For what purpose we are using Well TAP cells?

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For what purpose we are using Well TAP cells?

Any one clearly explain this one Pleaseeeeeeeeee
 

The CMOS FETs are actually 4 terminal devices, source, gate, drain and body. TAP cells provide a low resistance connection path to the body. In digital circuits, body of MOSFETs are usually connected to the power or ground. That is why if you look closely at the digital P&R layout, you'll see the TAP cells are usually on the power rails of standard cells.
 
tap cells gives reverse bias to the nwell and p well .
This is to avoid latchup

latch up in simple words is , phenominon where the the thyristor formed by adjacent junctions in the substrate turns on and goes to
a high curret mode ( thermal run away)
 
Nowadays, Standard cells do not have internal tap to N well (P substrate process) to reduce design complexity of standard cells. Hence tap to wells is done by external cells called "TAP cells". These TAP cells are sprinkled all over core area at regular distance (decided by foundry).
 

It is also a "marketing" aspect. The cell vendor could included enough bulk connection in each std cell, but these one will have theis size increased. Then, the bulk connection is "removed" and it did not mention the necessity to add the well tap on your design...
in 65nm TSCM, the well tap need to be placed at least each 30um, and the well tap width is 0.6um, rougly 3% of row area.
 

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