How to Use TSMC 0.18um Process and BSIM3(V3.1) Model

Hi! I'm a newbie in analog design. I'm currently designing a schematic of a two-stage cmos opamp using TSMC 0.18 process file and BSIM3(V3.1) model as my library in Star-Hspice simulator. Using the formula for Id(sat) and the parameters(Vt0, tox, Uo) from my model, I was able to compute W/L to achieve the 80dB open loop gain. But during ac simulation the result is -40dB. What could be the problem in my design?...Does it means that hand calculation using the Vto, tox and Uo parameters will not give me my expected/computed result during simulation? Then how should I use those parameters and model in my design during hand calculation to achieve my expected output? Please help me. Thanks!

I am not expert .... But I think you will not get the expected output (from manual calculations) from the simulation. You can calculate only approx. gain from manual calculations. But the difference between the two will not be as large as 80 dB and -40 dB. I think there is some problem with simulation ( netlist ) ....

Hi himansg. Thank you very much for ur reply... So far my netlist is ok since when i try to dc sweep my negative input I have a correct dc transfer curve. During dc sweep my op-amp acts like a comparator. Therefore my netlist is correct right?.. So how would i use TSMC 0.18um process file and BSIM3(V3.1) model in my design? Any advice on how to start my design? Should I do the hand calculations first or proceed immediately to netlisting. I already have a schematic configuration though. Your opinion and advice will be very much appreciated. Thanks.

I have done similar work in Hspice. to use TSMC process file , you will have to give transistor model name in you netlist ... (by using either .lib or .include depending upon your process file )... have you done that ??? and check that you have connected correct AC source ... it will better if you attach your netlist here ...

This might be pretty basic, but are you sure you're doing your AC analysis with the proper DC biasing? Are all your transistors in saturation when doing a DC operating point analysis? Having a valid DC sweep of the input doesn't mean anything if you're not biasing the circuit for operation in the sloped part of the DC sweep.

Do AC with correct DC close loop feedback.

I was able to compute for W/L based on Gm with the use also of tox,uo and vtho parameters from my model.

My netlist below is configured as open loop without feedback. Do i have to employ a feedback to be able to run an ac simulation?...Is my vp and vm configurations correct to run an ac simulation and determine my open loop gain?

How can i check if my transistors are properly biased and or are operating in saturation? what type of simulation should i run?...i'm also a newbie in h-spice.

Thanks!

*****************
My Two-Stage Op-Amp Design
.options list node post
.op
.global vdd vss
.lib 'mm018.l' TT_3V
*Diff Amplifer
*W/L = 6.35
M1 3 vp 1 0 nch3 l=1.8u w=11.43u
M2 3 vm 2 0 nch3 l=1.8u w=11.43u
*W/L = 14.65
M3 vdd 1 1 vdd pch3 l=1.8u w=26.38u
M4 vdd 1 2 vdd pch3 l=1.8u w=26.38u
* W/L = 10
M5 0 4 3 0 nch3 l=1.8u w=18u
*Common Source Out
*W/L = 55.55 *Supposed to be W/L=88 but the Wmax=101u only
*is it right by simply making w=100u???
M6 vdd 2 vout vdd pch3 l=1.8u w=100u
*W/L = 30
M7 0 4 vout 0 nch3 l=1.8u w=54u
*operating in triode region with R=.919kohms
*so w/l=7.5
Mr 2 0 5 vdd pch3 l=1.8u w=13.5u
Cc vout 5 3.3pF
CL vout 0 10pF
*Bias Ckt
iref vdd 4 33.33u
*W/L=10 same with M5 (curren mirror)
Mb 0 4 4 0 nch3 l=1.8u w=18u
*Sources
vdd vdd 0 DC 3.3V
vp vp 0 dc 1 ac 1
vm vm 0 dc 1 ac 0
.ac dec 100 1 1g
.probe vdb(vout) vdb(vp) vdb(vm) vdb(2)
.end

Yes for stability analysis. It needs DC feedback loop to decide correct operating point. Meanwhile, AC loop should be broken for open-loop gain and phase. Big inductor (like 10GH) provides DC path and blocks AC path.