amac5
Newbie level 3
Hi all,
I am somewhat new to FPGA design (most of my background is in analog electronics) and I am seeking guidance/advice on the best way to
1. Read a vector of data (text file generated in Matlab) into a Spartan-3E
2. Perform some computations on the data (like FFT)
3. Write the data back out to an output file on my PC to be read by MATLAB.
I am using VHDL in the ISE Webpack from Xilinx.
My main concern right now is getting the input/output part of this project working. What is the best way to do this? I have investigated using the STD.textio.all package to accomplish this. However, I have only been able to get a simple function working in simulation. It seems like something more advanced may be necessary to get this working on the FPGA (like writing to an actual block of RAM in the FPGA).
Here is my code that works in simulation:
Thanks in advance.
I am somewhat new to FPGA design (most of my background is in analog electronics) and I am seeking guidance/advice on the best way to
1. Read a vector of data (text file generated in Matlab) into a Spartan-3E
2. Perform some computations on the data (like FFT)
3. Write the data back out to an output file on my PC to be read by MATLAB.
I am using VHDL in the ISE Webpack from Xilinx.
My main concern right now is getting the input/output part of this project working. What is the best way to do this? I have investigated using the STD.textio.all package to accomplish this. However, I have only been able to get a simple function working in simulation. It seems like something more advanced may be necessary to get this working on the FPGA (like writing to an actual block of RAM in the FPGA).
Here is my code that works in simulation:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
entity textfile_io is
port(clk : in STD_LOGIC);
end textfile_io;
architecture i_o of textfile_io is
file in_file : text open read_mode is "input.txt";
file out_file : text open write_mode is "output.txt";
begin
file_io:
process (clk)
variable in_line : line;
variable out_line : line;
variable a, b : std_logic;
begin
while not endfile(in_file) loop
readline(in_file, in_line);
read(in_line, a);
b := NOT a;
write(out_line, b);
writeline(out_file, out_line);
end loop;
end process file_io;
end architecture i_o;Thanks in advance.
