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How to program RAM in Verilog ?

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G

Ghassan

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Hi all...
can anyone tell me how to program a RAM in verilog ?
i want to make 128-Deep by 14-Wide memory...
thx alot...
 

ram verilog

may be this example will help ?

Code: 
module verilog_dual_port_ram
(
    input [(D_WIDTH-1):0] data,
    input [(A_WIDTH-1):0] read_addr, write_addr,
    input we, clk,
    output reg [(D_WIDTH-1):0] q
);

 parameter D_WIDTH = ???;  //  your parameters
 parameter A_WIDTH = ???;

 reg [D_WIDTH-1:0] ram[2**A_WIDTH-1:0];

 always @ (posedge clk)
    begin
       if (we)
        ram[write_addr] <= data;
        q <= ram[read_addr];
    end

endmodule
---
 

dual port ram verilog

thx alooot
 

hi all hope you are fine
and sir "j_andr" i've been working on FPGA based projects can you tell me your email address....................:)
 
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