How to generate a look-up table from MATLAB on FPGA in Verilog?

hi dear all...
I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog?
I know that should be use a block-RAM, but I don't know how to write verilog code. please help me.
the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it correct? please help...

Please answer me...

Amir.B said:

Please answer me...

Click to expand...

Hi, you idea is right. While verilog is not the same as matlab, you do need some knowledge about verilog and digital design and FPGA.

use vhdl/verilog language templates in your system. For a example Xilinx ISE has a good set of hdl synthesis templates(counters, block ram, ...). if you know a little of verilog i will understande.

Block Dual RAM :
parameter RAM_WIDTH = <ram_width>;
parameter RAM_ADDR_BITS = <ram_addr_bits>;

(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] <output_data>;

<reg_or_wire> [RAM_ADDR_BITS-1:0] <read_address>, <write_address>;
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;

// The following code is only necessary if you wish to initialize the RAM
// contents via an external file (use $readmemb for binary data)
initial
$readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);

always @(posedge <clock>) begin
if (<write_enable>)
<ram_name>[<write_address>] <= <input_data>;
<output_data> <= <ram_name>[<read_address>];
end

---------- Post added at 16:35 ---------- Previous post was at 16:34 ----------

Pardon , "if you know a little of verilog i will understande" -> if you know a little of verilog YOU will understand )

Thank you so much dear kirill, for your kind consideration...

i feel a small sarcasm in your sentence

No, No, Never...
Your guide was so useful for me, I say this seriously...
thanks, once again!