Simple 8 bit ALU in Verilog needed

Hey guys, this is my first and hopefully not my last post. I'm a noob in verilog and also seems that i'm pretty much stupid :-( because i need a simple 8 bit ALU code and i need it tomorrow is there anyone that can help me?

You can start from this code:

module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;

reg [7:0] outp;

always @(posedge clk)
begin
case (opcode)
3'h0 : outp <= a + b;
3'h1 : outp <= a - b;
3'h2 : outp <= a & b;
3'h3 : outp <= a | b;
3'h4 : outp <= ~a;
endcase
end
endmodule


but i need to add a carry and a function in case of 0 (zero) to it, which i don't know how.

and if anyone can point me in the direction of a diagram for it, I'd be forever in your debt.

Thank you in advance to anyone that can help.

Hi Courage,
This is good enough to start, well attempt.
Use concate operator {} with the ADD function to achieve the carry. I dont know the indention of using logical AND (&), OR (|), and NEGATION (~).
Instead you can use the MULTIPLICATION (*), DIVISION (/) operators if the indention is ALU. Take little care while doing DIVISION (Avoid divide by ZERO). Hope this may help you.

-paulki

sincerely? i didn't understand half of what you said. When i said i was a "noob" i meant "TOTAL NOOB". So if you could help me out with the code i would be so much in debt

Try first with the operators I've mentioned instead of AND, OR, NOT functions. Simulate and you'll gradually understand thing better by experiencing. Still u face issues post it.
Take care while doing MULTIPLICATION, the result (outp) should capable of storing the result, I mean the WIDTH should match for storing the OUTPUT result of MULTIPLIED result, here this should be incresed from 8bit to higher in the range of 10bit or 16bit. Then no need to take care about the CARRY Overflow issue.

Adding some googled result... You can still extend the function with MULTIPLICATION (*) and DIVISION (/) operation, this may help you designing robust ALU functionality

module alu(a,b,cin,alu,carry,zero,ctl);

input [3:0] a,b; // port A,B
input cin ; // carry input from carry flag register
output [3:0] alu; // the result
output carry; // carry output
output zero ; // zero output
input [3:0] ctl ; // functionality control for ALU
wire [4:0] result; // ALU result

assign result = alu_out(a,b,cin,ctl);
assign alu = result[3:0];
assign carry = result[4] ;
assign zero = z_flag(result) ;

function [4:0] alu_out;
input [3:0] a,b ;
input cin ;
input [3:0] ctl ;
case ( ctl )
4'b0000: alu_out=b; // select data on port B
4'b0001: alu_out=b+4'b0001 ; // increment data on port B
4'b0010: alu_out=b-4'b0001 ; // decrement data on port B
4'b0011: alu_out=a+b; // ADD without CARRY
4'b0100: alu_out=a+b+cin; // ADD with CARRY
4'b0101: alu_out=a-b ; // SUB without BORROW
4'b0110: alu_out=a-b+(~cin); // SUB with BORROW
4'b0111: alu_out=a&b; // AND
4'b1000: alu_out=a|b; // OR
4'b1001: alu_out=a^b; // EXOR
4'b1010: alu_out={b[3:0],1'b0}; // Shift Left
4'b1011: alu_out={b[0],1'b0,b[3:1]}; // Shift Right
4'b1100: alu_out={b[3:0],cin}; // Rotate Left
4'b1101: alu_out={b[0],cin,b[3:1]}; // Rotate Right
default : begin
alu_out=9'bxxxxxxxxx;
$display("Illegal CTL detected!!");
end
endcase /* {...,...,...} is for the concatenation.
{ADD_WITH_CARRY,SUB_WITH_BORROW}==2'b11 is used
to force the CARRY==1 for the increment operation */
endfunction // end of function "result"

function z_flag ;
input [4:0] a4 ;
begin
z_flag = ^(a4[0]|a4[1]|a4[2]|a4[3]) ; // zero flag check for a4
end
endfunction

endmodule

WOW. Thank you very much.

Now if I would want to turn that into a 4bit ALU what would have to change?

Just one thing I would like to emphasize from my experience in verilog coding style:

For case statement always use "default" statement, when not all states are being used. This is very important to have good results in synthesis phase.

Thank you to both of you for your tips and help. Really helped a lot.
Thank you again