Blocking and Non- Blocking

Hi All,

Can anybody tell How many flops will be there in this logic.

always @ (posedge clk)

b = a;
c = b;
d = c;

endalways


always @ (posedge clk)

b <= a;
c <= b;
d <= c;

endalways

How are the outputs defined reg or wire?

As far as I know the blocking assignments are not synthesysble. Hence the first flop syntax is not correct.

I am not sure. The blocking case will have 1 f/f and the non bloking case will have 3 f/f. Please wait for others to confirm.

I would agree with 1 FF for the first and 3 FF for the second, if equivalent FFs are trimed by the synthesizer.

If you are an engineer or a would-be engineer, try to learn how to find the answer by yourself.
Running simulation or synthesis will give you an immediate answer.

the first one: 1 FF
the seconde one: 3 FF

Hi,

http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

see page 9

Hi,friend
Reading the veriligHDL book introducing the excution machenism about "=" and "<=" ;
From the software repect , how the VerilogHDL Compiler is working? decided by the Compiler itself.
For "=" :
Compiler excution start:
1st step : excute the b=a; time 0 -> 5(assume)
2nd step : excute the c=b; time 5 -> 10(assume)
3st step : excute the d =c; time 10 ->15(assume)
Compiler excution finished!
Ok, at time 15 d=a; The Compiler will give the last result :
d value given by a. <--------------
VS
For "<="
At the same time
excution start: posedge clk ,time 0
b<=a; time 0-6
c<=b; time 0-6
d<=c; time 0-6
excution finished! time 6
Now the Compiler need to considering these following cases:
b value given by a ;<------
c value given by b ;<------
d value given by c ;<------
The above analysis is considered from the behavior of the Compiler.
Of course, the behavior of the above Compiler is designed justly for verilogHDL used for describing the didital logical circuit.
The behavior of the Compiler will be reflected to the hardware, and it just needing 1 and 3 store cells for the "=" and "<=" case separately.

@ qieda, i thought it had syntax error at firstly, and now i see. It will be synthesied as a DFF . Good!