Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

new questions from nvidia

Status
Not open for further replies.
R

rakko

Full Member level 4
Full Member level 4
Joined
Jun 1, 2001
Messages
233
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,298
Location
mozambic
Activity points
2,065
2- How many bits do you need if you are adding two 8-bit numbers? How many for 3 8-bit numbers or 4 8-bit numbers?

3- When you are verifying a design at what point do you decide that verification is done and the design can be released?

4- What are the different areas of code coverage? list them.

5- Why is it important to fix transition time even if there are no timing issues?

6- What is your reset strategy?

7- what are the disadvantages of Verilog as an HDL language?

8- What are the advantages/dis-advantages of synchronous vs. async resets?

9- If you have two blocks running at 50 Mhz each and one block of the same gate size, as the two 50 mhz ones, running at 100 Mhz, which one uses less power? Assume voltages are identical.

10- What is your power strategy?

11- What are the challenges of porting a design into an FPGA?

12- How do you fix hold time violations in FPGAs?
 

HI,reading the follwoing ,maybe helpful for the test in the future.
2 : 1111_1111 + 1111_1111 = sum-width; 1111_1111 + 1111_1111 =？ 1111_1111 + 1111_1111 + 1111_1111 = ？
3: NO DONE TIME i think. just better,no best. U should try your best to find the debug of the system, even if it can realize the function according to the spec.
4: if...else / case / loop / sentences/...
5： SI. If not fixed ,it maybe induce crossdelay and croostalk problem at the later step.
6: synchoronous reset is better at ASIC/hard reset and soft reset choosing/RECOVERY&REMOVE
7: its architecture is not as good as vhdl at the system level.
8: async reset maybe induce metability.sync reset you should control the reset pulse width is long enough.
9:
10: so many ,containing: system/algorithm/coding/gate/physical level. Optimize architecture,algorithm,analog circuit/MEMORY Choosing/diffrent working mode(Normal Sleep Doze RTC)/Clock Gate/POWER Gate/plex skill/use low power lib/DFMS/special gate logic tech/HVT cell firstly using/.....Of course you should have a balance considering other repects ,like speed/cost/timing/time-market.
11 : resourse capacity/fpga speed/USE IP CORGEN fully/.
12: ?

---------- Post added at 14:17 ---------- Previous post was at 13:35 ----------

9: 100MHZ power 2 * 1 / 50mhz power 2 * 2 = 2; yeah the 100mhz system cost more power .
the above is just my opnion,u'd better have a talk with others, maybe have a right or deep understanding.
 
Hi rakko,

after considerable work from sunjianhuigou i am left with question 12

12>Xilinx has addressed this problem by adding a deliberate delay to every FPGA data input. In some FPGAs, this delay is fixed and always present and in others this delay is optional and depends on clock distribution delay. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

As a result no Xilinx FPGA Data input has a hold-time problem when the design uses the internal global clock distribution network. This problem occurs only if we are trying to use clock gating circuits...so avoid those in your hdl code or use the optional delay available on your input data path to meet the hold requirement. You can also Change constraints on the clock so that it is distributed with low delay

Useful???
 
Last edited:
Thanks phoenixpavan. So that's how FPGA handles I-R path. How about R-R path when it has hold violation?
 

2- How many bits do you need if you are adding two 8-bit numbers? How many for 3 8-bit numbers or 4 8-bit numbers?
Click to expand...

the result of adding two 8bit numbers is 9bit. -> you would need 9bit adder
the result of adding three 8bit numbers is 10bit. -> you would need 10bit adder
the result of adding four 8bit numbers is 10bit. -> you would need 10bit adder

4- What are the different areas of code coverage? list them.
Click to expand...

block coverage, which look whether all line of code are used
expression coverage, which looks whether all combination of inputs are used in an expression
toggle coverage, which looks whether every signal has reached 0 and 1


9- If you have two blocks running at 50 Mhz each and one block of the same gate size, as the two 50 mhz ones, running at 100 Mhz, which one uses less power? Assume voltages are identical.
Click to expand...

I think power goes linear with frequency -> both design are equal regarding power.

regards
 

sunjianhuigou said:
HI,reading the follwoing ,maybe helpful for the test in the future.
2 : 1111_1111 + 1111_1111 = sum-width; 1111_1111 + 1111_1111 =？ 1111_1111 + 1111_1111 + 1111_1111 = ？
3: NO DONE TIME i think. just better,no best. U should try your best to find the debug of the system, even if it can realize the function according to the spec.
>>> I think it shouldn't be "no done time". You know, for a company, time to market is very important. Therefore, for verification engineer, you should try to verify the as fast as you can.

4: if...else / case / loop / sentences/...
5： SI. If not fixed ,it maybe induce crossdelay and croostalk problem at the later step.
6: synchoronous reset is better at ASIC/hard reset and soft reset choosing/RECOVERY&REMOVE


7: its architecture is not as good as vhdl at the system level.
>>> What do you mean the system level? Currently the systemverilog is release, it combined VHDL a lot of VHDL features in it.

8: async reset maybe induce metability.sync reset you should control the reset pulse width is long enough.
>>> No matter how long it is. you can avoid the metability.

9:
>>> it should have an equation there, but I forgot it. It seems to be related to square of frequency.

10: so many ,containing: system/algorithm/coding/gate/physical level. Optimize architecture,algorithm,analog circuit/MEMORY Choosing/diffrent working mode(Normal Sleep Doze RTC)/Clock Gate/POWER Gate/plex skill/use low power lib/DFMS/special gate logic tech/HVT cell firstly using/.....Of course you should have a balance considering other repects ,like speed/cost/timing/time-market.
11 : resourse capacity/fpga speed/USE IP CORGEN fully/.
12: ?

---------- Post added at 14:17 ---------- Previous post was at 13:35 ----------

9: 100MHZ power 2 * 1 / 50mhz power 2 * 2 = 2; yeah the 100mhz system cost more power .
the above is just my opnion,u'd better have a talk with others, maybe have a right or deep understanding.
Click to expand...

Is question 2 means 9, 9, 10 bits?
 

enchanter said:
Is question 2 means 9, 9, 10 bits?
Click to expand...
soory.
had made a mistake there,
it is 2/3/4 8 bits adders separately. the result is 2 adders:9, 3:10, 4:10.

---------- Post added at 08:17 ---------- Previous post was at 07:56 ----------
enchanter said:
Is question 2 means 9, 9, 10 bits?
Click to expand...

Hi,
qieda

7 :::::: the system level or gate level just from the language architeture,eg, at VHDL , describe the circuit with keywords:
ENTITY, ARCHITECTURE, PROCESS ,but at veriloghdl , it's just always&assign sentence,the reader can't see the hierarchical infomation from the language quickly. i think so.
8 ::::::: what i mean is that asynchoronous reset will induce metability problem,but synchoronous will reduce the problem.
And when using the synchoronous reset, should make sure that the reset is captured by the clock , so it should be at least one clock period.
9:::::::: power = C * F power (2) * xxx .
 

Hi sunjianhuigou

I do not agree

9:::::::: power = C * F power (2) * xxx .
Click to expand...

Pdynamic = C·V²·f

I think
power scales linear with frequency and quadratic with supply voltage

regards
 
qieda said:
Hi sunjianhuigou

I do not agree



Pdynamic = C·V²·f

I think
power scales linear with frequency and quadratic with supply voltage

regards
Click to expand...

ok , i remembered it as = v*c*F power(2). [it's wrong!!]
yes, you are right .
 


Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top