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[SOLVED] Verilog synthesis problem!Please Help

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UFK

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Dear Verilog users

Please help me synthesize a simple Verilog program which calculates the log base 2 of a value.

My code is

module Log_max(v,n_var,T);

input [31:0]v;
output [31:0]n_var;
output reg [31:0] T=0;
wire [31:0] v;
reg [31:0]n_var;
reg [3:0] base = 2;


//floor of the log base 2
function integer CLogB2;
input [31:0] Depth;
reg i;
begin
i = Depth;
for(CLogB2 = 0; i > 1; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction

always @ (v)
begin
n_var = CLogB2(v);
T = 2 ** n_var;
end
endmodule
Click to expand...

The testbench is

module Log_max_tb;

// Inputs
reg [31:0] v;

// Outputs
wire [31:0] n_var;
wire [31:0] T;


// Instantiate the Unit Under Test (UUT)
Log_max uut (
.v(v),
.n_var(n_var),
.T(T)
);

initial begin
v = 2614;

end



endmodule
Click to expand...

If i use the datatype reg for variable 'i' the program synthesizes but does not give results. Please help me synthesize this code.

Thankyou
 

Hi UFK,
Any "for-loop" which is intended to be Synthesizable, should be "fixed" number. Here your input "Depth" is directly assigning to the "i" value.
If you need to get synthesised output either do parameterise the "i" value or assign a known value to "i". Typically synthesis tools will optimize the for loop which is not fixed increment.
I didnt synthesize, only first cut analysis.

-paulki
 
Hi paulki

Thanks for your help. I tried what u suggested and my code calculates the value correctly but it still does not synthesize. I gave a constant value to the variable 'i'. It gives me the same error which is

ERROR:Xst:2634 - "Log_max.v" line 37: For loop stop condition should depend on loop variable or be static.

Please suggest what i can do to synthesize it.

Thankyou
 

I think you're missing the 'begin' and 'end' keywords that should enclose the code inside the for loop. Try that and see if that helps.

--Rohit
 

To detect the highest 1-bit in a vector of width 32, you have to set up a loop with a fixed number of 32 iterations. You can exit it, when the scan is finished. You missed to give reg i the required width, by the way.

I think you're missing the 'begin' and 'end' keywords that should enclose the code inside the for loop.
Click to expand...
Similar to C {} brackets, begin .. end is needed with more than on instructions in the loop. In this case it isn't.
 

Thanks Fvm.
I understand what you suggested and i tried it in my code. It gives correct results and synthesizes too. But it just gives a 96% Bonded IO result and 0% slice utilization which leads me to think there is a problem which the simulator cant comprehend.
Im posting my code and testbench. Please suggest what i can do to get it working.

module Log_max(v,n_var,T,clk);

input clk;
input [31:0]v;
output [31:0]n_var;
output reg [31:0] T;
wire [31:0] v;
reg [31:0]n_var;
//reg [3:0] base = 2;

//floor of the log base 2

function integer CLogB2;
input [31:0] Depth; //pseudo input port which remains unused throughout the program
integer i;
begin
//i = Depth;
i= 2614;
for(CLogB2 = 0; i > 1; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction

always @ (posedge clk)
begin
n_var = CLogB2(v);
//T = base ** n_var; This is unsynthesizable. Can only be simulated

T = 2 ** n_var;


end
endmodule
Click to expand...


And the testbench

module Log_max_tb;

// Inputs
reg [31:0] v;
reg clk;

// Outputs
wire [31:0] n_var;
wire [31:0] T;

// Instantiate the Unit Under Test (UUT)
Log_max uut (
.v(v),
.n_var(n_var),
.T(T),
.clk(clk)
);

initial begin
// Initialize Inputs
v = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;

v = 2614;
clk = 1;


end
endmodule
Click to expand...

Thanks alot for your suggestion.
 

The new code doesn't calculate anything because the output doesn't depend on input data.

The original code most likely works if you replace reg i by integer i;
 

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