Damage microcontroller by driving FET directly with output pin?

Hello,

Will we damage our Freescale MC9S08AC60CFGE microcontroller by driving a FET from a microcontroller output pin, with no series resistor?




We are powering solenoids via switch-mode solenoid drivers which comprise FETs being driven directly from a microcontroller.
-as stated , the FET gates are being driven directly from the microcontroller pins, with no series resistor used. (-the microcontroller is supplied from 5V)

Here is the schematic:

SCHEMATIC:
https://i53.tinypic.com/1zm1j08.jpg


Here is the gate charge current…….please notice that it goes up to 450mA , -though the gate charge pulse is only for 103ns (the switching frequency is 20KHz)
…I represented the output resistance of the microcontroller pin as 5R, though in truth , I don’t know what it is, and the datasheet does not state it.

GATE CHARGE CURRENT:
https://i52.tinypic.com/9a1yyr.jpg


Page 304 of the MC9S08AC60CFGE microcontroller datasheet states that the maximum instantaneous current allowable in a microcontroller pin is 25mA

Page 304 of MC9S08AC60CFGE microcontroller datasheet:

https://i51.tinypic.com/4rtj00.jpg



Also of interest , is that page 307 of the MC9S08AC60CFGE microcontroller datasheet states that the latch up current is 100mA…….so does this mean that we will be risking latch-up?....since our gate drive current pulses go up to 450mA…..

Page 307 of MC9S08AC60CFGE microcontroller datasheet:

https://i51.tinypic.com/fmq61k.jpg



MICROCONTROLLER DATASHEET (Freescale MC9S08AC60CFGE):
https://cache.freescale.com/files/microcontrollers/doc/data_sheet/MC9S08AC60.pdf?fsrch=1&sr=5

FET DATASHEET (STB16NF06LT4):
https://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00002847.pdf

You can check the graphs in page 310 of the mcu manual.
You will see there that when you pull current you have a rapid voltage drop, so for example with a Vcc=5v and 20mA pin current the actual output will be 3v(graph shown the voltage drop which is 2v),
if you want to simulate that use a feed 5v to the gate through a resistor of 100 ohm.
This can't work correctly, you will have many loses in the mosfet because of the slow switching (slow gate charge).
This will probably be bad for the mcu too because it stresses the output stage.

https://ww1.microchip.com/downloads/en/AppNotes/00786a.pdf

Alex

To bring in a pleasing news, latch-up is only triggered by driving current through parasitic transistor structures, which implies driving pins beyond the supply rails. Fortunately, this doesn't happen with capacitive loads. But that's the only good news, I fear.

You're effectively asking, if maximum ratings can be simply ignored, and what happens if you do. Seriously, noone can tell for sure. So as the most simple answer: It's bad engineering practice, don't do it. In this case, there's no real need to ignore the specification, except perhaps recycling a careless designed board. The problem is however, that instantaneous current and power data may be simply guessed by a designer without thorough measurements or calculations. If you have a e.g. full characteristics of power transistors or diodes with detailed impulse current versus time duration and repetition count charts, I would expect that they are well founded. If you get a single bare number for peak current, it's possibly not the case. But you can't know.

P.S.: I looked at the electrical characteristics in the datasheet and found, that the Freescale processor implements a software drive strength setting. According to the graph, the typical output resistance is around 100 ohm for high and 300 ohm for low. This means, that setting the drive strength to low already keeps the instantaneous current rating for a single pin. Another question is, if you'll be happy with the slow slew-rate driven to the gate and respective FET output switching.

In addition, the existence of the high drive settings partly questions an absolute 25 mA limit, because it will be exceeded for a few 10 ns even with moderate capacitive loads.

I don't think there is any chance to get even 100ma from an output with these characteristics, the mcu output shows an impedance of about 100 ohm so it will barely go over 50mA before the output is 0v



Alex

so it will barely go over 50mA before the output is 0v

Click to expand...

Yes, exactly. But the value still exceeds the maximum ratings. The latch-up value of 100 mA isn't relevant anyway, because it's in the clamp quadrant of the output characteristics, not in the pull-up/pull-down.

I wrote it as an addition to your post because in your answer you said

...If you get a single bare number for peak current, it's possibly not the case. But you can't know.

Click to expand...

This was your answer for the simulation peak gate current at that time but
then you read the datasheet and added the P.S. part but i read it after my second post, so when i wrote this it was an answer to the above statement without the P.S. part.
I'm not suggesting that he can or should use the circuit with there parameters.

Alex

The bare number from the data sheet is 25 mA, so the problem still exists with 100 ohm output impedance.

Hi,

I have presented to the boss that we need to change this circuit , but he is not convinced.

Only a few of the actual product was ever sold because we had an issue with a connector failing a glo-wire test, due to it not being made of flame-proof plastic.

We are due to re-start production of this product in 6 months.

My boss is pointing out that the total gate charge Qg for the FET is just 10nC.

He is asking also, what is the amplification of the gate capacitance by the Miller effect.

The datasheet gives the Qg as 10nC for a 48V bus........ours is 36V so we will get less Miller" capacitance magnification.....................for the 48V bus , the overall capacitance is around 2.2nF (including miller effect).

I have to convince my boss that this is too much for a switch mode solenoid driver driven dircetly from a uC port.

....In the actual product, the uC drives four FETs. (no series gate resistor and no gate driver)

...people at the factory are telling me i am crying wolf.

..they say that this product successfully went through a lot of qualification testing.

I wonder who they are going to blame if the product fails, it can't be you because you have waned them of the problem,
on the other hand they may blame you because you knew what was wrong and you didn't stop them from making that mistake...:???:

Did you simulate the circuit with the 100R gate resistor (which is still in the limit of the max specified current ),this will show a behavior similar to the real mce output,
how were the results, if they fit your needs then just add the resistor but using no resistor at all doest seem right.
Since the mcu will drive 4 mosfets use one 100 ohm resistor and feed all 4 gate trough it, are the results still satisfactory?

Alex

Hi
with a 100R gate resistor, the FET gate current (= microcontroller pin output current) is a train of spikes, each one above the 25mA instantaneous current limit of the microcontroller.

FET gate current with 100R series resistance (100R represents the microcontroller's suggested output ressitance):-

https://i53.tinypic.com/o60bkn.jpg


do you consider that this current is unnaceptable?

You could increase the series resistor to a value that keeps the 25 mA.

hi
I think your controller must be want feed back voltage and if your feed back voltage is very low then controller going to fet full on
and that is the resen of you fet blowing I think not sure please check your feed back voltage and also insert 330 ohm resistance in gate series and
one resistance 10 K must be insert the source end i think then you cover the the problem ( one more tip for fet insert the one zener on gate to source
he save the your fet blowing

that is the resen of you fet blowing

Click to expand...

Nothing has been said about blown FETs.

The maximum gate current can be limited to a value close to the mcu max but you should also look the pulses at the mosfet drain for a correct shape,
also use the current and voltage drop of the mosfet to draw a power consumption graph.
Driving a mosfet gate with a low current will result in low rising and falling time for the output pulse
and will also increase the heat consumed on the mosfet because of the slow turn on/off (transition period).
It would probably be best to check the real circuit, measure the temperature of the mosfet after it has worked for a while and also use an oscilloscope to see the output.
If your real circuit is without the gate resistor then the current pulses will create some additional heat to the mcu so check that too.

Alex

You're right about increased losses with higher gate resistance, but curiously eem2am didn't telll any requirements in this regard, so I assume, low frequency PWM is intended. He's long enough in the business to know about switching losses. I think, operating a FET from a uC directly is a decision for low speed switching, possibly accepting some losses. Otherwise, one would use a gate driver.

In the first post he said that the the switching frequency in the simulation was 20KHz,
this is probably the real switching frequency too.

Here is the gate charge current…….please notice that it goes up to 450mA , -though the gate charge pulse is only for 103ns (the switching frequency is 20KHz)

Click to expand...

Alex

Yes, 20 kHz isn't low. With 100 or 200 ohm gate resistor, you get gate current rise- and fall times of several 100 ns, so the switching losses will be in a percent of load power order of magnitude at 20 kHz. But a more exact value can be easily derived from the simulations.