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fpga lvds, mini lvds spartan 3A dsp board clock

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I am using a spartan 3A dsp board clock to the board is 100Mhz but the manual says all differential i/o are working more than 662 Mhz, how it can be?
 

Re: fpga lvds, mini lvds

It's the general board clock.
But it meant to say that signals that have 662 MHz frequency can be sampled or can be outputted from these differential I/Os.
Not every design can work at 662 MHz so they put an oscillator for 100 MHz..
 
ok does there exist any high speed clock on fpga board to which 662 Mhz differential signal is synchronized to.
 

I have never seen such fpga demo board which has 662MHz on-board clock...
These kind of boards are complex and expert ones...

Let me explain you the situation : The companies or someone who needs an expert application, can build their PCBs according to their needs. So if they need to operate differential IOs of FPGA, they put an oscillator on their PCB design.

But such as me and you :) actually don't need these kind of applications, so companies who design FPGA demo boards, don't care about differential IOs maximum operating frequency while designing.
 

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ok thanks this must be the situation. we were looking for testing a high speed DAC requiring data input at 500 Mhz and having 48 channels of data in testing equipments are very costly so we were looking at FPGA board for a cheaper solution.
 

Actually, you can test your equipment with FPGA demo board.

Search for DCM/PLL structures on FPGA over Internet..
You can upconvert your on-board clock(for eq : 100MHz) by using DCM to 500MHz or applicable frequencies..

As a result, you can achieve what you have explained by using DCM on FPGA.
But DCM structure is dependent to FPGA technology, so be aware of this.
 

The said 6xx MHz frequency is for the data rate of high speed serial outputs. The maximum DCM and clock pin output frequency is only half of it. So you would be able to generate a 500 MS/s data stream with a 250 MHz core clock, but you can't drive a 500 MHz clock output, if your DAC requires it (a MAX5888 e.g. would).
 



A 500 MSPS data will have a bit period of 1/500 e6 = 2 ns .
If data is latched at +ve edge of clock than clock should have 1 ns of on period and 1 ns of off period ok immaterial of duty cycle it should complete one cycle in 2 ns since time period of clock is 2 ns so clock frequency comes to be 1/2ns = 500 Mhz.

A 250 Mhz clock will have a time period of 4ns if this clock is used to latch data my data is going to change every 4 ns which comes to be 1/4ns = 250 MSPS or 125 Mhz.
 

A 500 MSPS data will have a bit period of 1/500 e6 = 2 ns .
If data is latched at +ve edge of clock than clock should have 1 ns of on period and 1 ns of off period ok immaterial of duty cycle it should complete one cycle in 2 ns since time period of clock is 2 ns so clock frequency comes to be 1/2ns = 500 Mhz.
Click to expand...
That's correct, if the data is latched at one edge only. The high speed output on FPGA like Spartan 3A is provided by DDR (double data rate) registers, multiplexing two data lines to one output pin. So it can generate 500 MS/s with 250 MHz core clock. But I fear, the DAC needs a true 500 MHz clock, that can't be generated by Spartan 3A.

But
 

ok if spartan board is using DDR register than it will latch at both edges of clock than its ok.
My dac requires 48 channels of data at 500 MSPS. however frontend of my dac is a lvds rx and a latch this latch needs a clock of 500Mhz this clock we were planning to give through external source. to synchronize clock with data we are considering lvds rx transmission delay 400ps so this much delay ahead to the input data we are planning to give external clock. won't this will work?
 

The external source has to be synchronized with a Spartan output clock or input clock and you need a means for an initial delay adjustment, e.g. by programming the Spartan DCM accordingly. You should however check the Spartan specification for expectable delay skew.

From the Spartan perspective, it would be best, to generate a 250 MHz (respectively a fraction of it) clock parallel to the data and have a precise external PLL to generate 500 MHz from it.

I have designed systems, where 500 MHz clock and data are sourced from the same (Stratix II) FPGA, which is rather easy.
 
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