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slack optimization using RTL compiler

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srini.pes

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hi to all...........
i am doing project in ASIC design,
i have a slack of negative value (negative slack). am using cadence RTL compiler
in order to minimize this negative slack.........we have methods like buffer insertion and gate resizing.
am interested in using gate resizing but am not able to find the related constraints in that cadence RTL compiler....
if any one is working in this domain please guide me.....hoe to increase the size of a particular gate or a component.
thanking you all
 

Hi srini,
By default tool will choose best possible size of the gates to meet timing.make sure you are doing incremental optimization as well before you report violating paths.
 
It is automatically done for you. Just make sure your library contains multiple versions of each gate.
 
Respected Sri
i want to change my slack from negative to a small +ve value
For that one in cadence What to do
Like set_output_delay, set_input_delay, path_adjust.....
If u know about these things please give suggestions to me
Waiting for u r valueble reply
Thank you soo much
 

these delays you mentioned are project specific and should be calculated. they are not supposed to be changed in order to accommodate for any slack value.

have you tried asking the tool to perform synthesis using a high effort? have you tried to give timing a higher importance regarding area or power? these two might help.
 

respected
If synthesis effort high also it giving some negative slack
Thank you
 

the most radical thing to do is to change the actual project. find out which is the longest path, try to find the reason why it is the longest one and try to simplify it.

if your project is somewhat academic and it wont get fab, just change the input delay to a negative number. this will fix the slack but it will probably make your circuit not to work properly
 

R u seeing negative slack for register to register paths even with synthesis effort of high ? If so you need to change the clk period or change the design to meet those paths.
If negative slack is on Input to register or from register to output then adjust your IO delays to see positive slack . Normally you need to bother much about negative slack on Input to register or from register to output paths
 
Thank u so much for u r suggestion
I will try to modify it
Thank u Sri...
 

chiplogic said:
R u seeing negative slack for register to register paths even with synthesis effort of high ? If so you need to change the clk period or change the design to meet those paths.
If negative slack is on Input to register or from register to output then adjust your IO delays to see positive slack . Normally you need to bother much about negative slack on Input to register or from register to output paths
Click to expand...

I am getting negative slack in the path from Reg-Reg, that to a value of -16.5 ns with a clock period of 10 ns.........
please suggest me some models to overcome this
 

can you check whether it is cross clock path ?
If not you need to change the logic ..
Do you that much combo logic between two flops ?
which technology libs ?

Thanks
Sri
 

Respected sri....
you mean cross clock path means, having different clocks in the same design
if so, am having only one clock........
and my critical path is having combination logic in between flip flops.........
if u dnt mine can u give u r mail id..... i wil contact u through mail
and i will send my timing path also
please help me
 

Hi,

As u r having a slack of -16.5 ns in 10ns clk period which is more than a clock period, the tool high effort and other simple change of gates or buffering the path wouldn't help much, as there is a huge slack and the tool can only minimize upto certain point. The other options wud be change the design i.e creating a addition latency and/or adjust the combination logic with the next clock (as such retiming) ....etc etc.

Best Regards
 

Hi Srini,

I am not sure , if you are still struggling with the issue.

Before looking into the timing slack numbers,

make sure you have the right constraints
1) proper clock definitions in correct units( DC standard unit is ns , RC standard unit of period is ps )
2) Clock exceptions
3) Design Exceptions
4) Dont USE cells
5) How are the Datapath modules are mapped in your design?
6) Input / Output constraints
7) Number of Logic Levels between stage to stage ( It shouldn't be unreasonable )
8) Once all the above are thoroughly checked, then you can see the timing paths..
a) Are the timing path violations are due to high fanout nets ?
b) Any specific datapath architecure is eating up the frequency ?
c) How is the histogram of violations ?
9) initialtarget is nother command you can play with , if none of the above points help you!!


Hope this information may help you !!
 
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