Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

IC Layout:- Running LVS

Status
Not open for further replies.
20tech11

20tech11

Junior Member level 3
Junior Member level 3
Joined
Oct 23, 2010
Messages
26
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,283
Location
Edinburgh, Scotland
Activity points
1,444
Hi All,

I have a basic doubt may be it is stupid. I am working with the design of a 8 bit DAC and for better matching I have to follow common centroid geometry and have to add dummy elements. But when we run LVS will these dummy elements be considered as extra instances and Will the LVS show more instances in the Layout when compared to the original schematics.This means my original schematics and extracted schematics do not match at all.So how can I pass my LVS?

Thanks guys
 

you add dummy cells in your layout, so you must put the same dummy cells in your matching schematic.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top