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Low power VLSI design techniques

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blaze1200

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Hi,

My research is about low power design techniques.

-> Is it possible to use clock gating for DMA (asyn) ?
-> Other possible techniques besides clock gating ? (Preferably architecture/RTL)
-> Where can I obtain other testcase ? (> 10k gates + sync design)

Please advice. Advance thanks...
 

hi do you what are the recent trends in low power cmos vlsi design ...........

and what vlsi copmpanies require if we choose a project reg low power vlsi design
 

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