VLSI design verification

What is semi-formal and formal verification? why it is required and what is its importance?

Hi,

Formal verification is a systematic process that uses mathematical reasoning to verify that design intent (spec) is preserved in implementation (RTL). Jasper is the industry leader in formal verification. Jasper's formal solution algorithmically and exhaustively explores all possible input values over time. The overall verification can be started early in the design cycle while the RTL is being developed and can help in finding critical corner-case bugs which may be difficult to catch with simulation. Jasper's patented Visualize technology helps in visualizing the design with waveform views and can significantly accelerate design and debug without the need for a testbench or input stimulus.

Check out the following article on "What is Formal Verification" by Jasper...
**broken link removed**

Also check out the Jasper website for more info - --:: Jasper Design Automation::--

Let me know if you need any more specific info regarding formal verification....

Alok

Hi,
Thanks for the concern. I will check those websites. If any doubt i will get back to u.

---------- Post added at 01:42 ---------- Previous post was at 01:38 ----------

@ Alok: Just checked those links provided by you. Can u brief it up how semi formal and formal verification differ from each other.

Hi,

Semi-formal verification approach is not fully exhaustive and involves leveraging simulation in addition to the formal algorithms due to limitations with certain formal tools (mainly capacity to handle large designs). A fully formal verification solution such as Jasper's is 100% exhaustive with high capacity and does NOT require leveraging simulation to search deep into the search space.

Hope that helps.

Alok

formal verification solution is not suitable for algorithm logic,it's very long for tools run!

please elaborate on the kind of design and logic you were trying to use formal on...and was it a semi-formal or formal tool you were using...what were the kind of issues you encountered? More and more verification is now done with formal, especially to catch corner-case bugs which are tough to find with traditional verification methods....you can refer to some of these case studies and articles for specific applications and use of formal....

--:: JASPER ::--

Hi, am actually am not working on formal verification. Am a student pursuing my M.tech. So i wanted an over view of formal and semi-formal verification.