Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to fix setup violations

Status
Not open for further replies.
C

chanducs24

Member level 2
Member level 2
Joined
Oct 20, 2010
Messages
53
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,598
hi

after i ran CTS, i got setup violations with negative slack of 5ns. after CTSopt step, i got setup violations with negative slack of 2ns. can anyone suggest how to clear these setup violations in CTSopt?

Thanks,
chandra.
 

Are there setup violation during STA in frontend netlist?
If yes, you must rewrite RTL (reassembly critical pathes).
If no, you should probably reduce clock skew or use another wire load model during STA on frontend netlist.
 
  • Like
Reactions: yzseu

    Y

    yzseu

    Points: 2
    Helpful Answer Positive Rating
hi

what should we do to reduce clock skew.i'm using soc encounter.

Thanks,
chandra.
 

if you think them are real violation and you don't want to do synthesis again,you can replace the cell!
 

if real violation it should go back to frontend stage for coding/synthesis modification i think.
if just a very simple setup violation after analysis, you could do some trial. replace some cell with different loading/driving type which can decrease the delay of data path. or add delay cell to clock path of target register if you can borrow some timing margin from the next register on logic path.
 

5ns, it's very large.
sugession:
1. check your sdc file.
2. feek back this violation to your front end.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top