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how to fix setup violations

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chanducs24

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hi

after i ran CTS, i got setup violations with negative slack of 5ns. after CTSopt step, i got setup violations with negative slack of 2ns. can anyone suggest how to clear these setup violations in CTSopt?

Thanks,
chandra.
 

Are there setup violation during STA in frontend netlist?
If yes, you must rewrite RTL (reassembly critical pathes).
If no, you should probably reduce clock skew or use another wire load model during STA on frontend netlist.
 
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    yzseu

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hi

what should we do to reduce clock skew.i'm using soc encounter.

Thanks,
chandra.
 

if you think them are real violation and you don't want to do synthesis again,you can replace the cell!
 

if real violation it should go back to frontend stage for coding/synthesis modification i think.
if just a very simple setup violation after analysis, you could do some trial. replace some cell with different loading/driving type which can decrease the delay of data path. or add delay cell to clock path of target register if you can borrow some timing margin from the next register on logic path.
 

5ns, it's very large.
sugession:
1. check your sdc file.
2. feek back this violation to your front end.
 

5ns is quite high.
Did you check post-synthesis simulation?
If not then try to run and check the worst case scenarios.
 
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