Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

2 bit counter as finite state machine

Status
Not open for further replies.
As long as you know what state flows into what and all states are accounted for, the above link will help you out.
 
Sir the link provided by you gives some error and sir i am beginner in this field so please tell me steps in active hdl software. is the type state_type is (s0,s1,s2,s3); and signal current_s,next_s: state_type; is declared in where the inputs and outputs are declared. Please help i will require urgently......... please please help
 

Sir I have trying for coding of 2 bit updown counter as finite state machine. Now there is problem in my coding, and i am also confused about the input parameter to be used in this case. I have using active hdl software for coding of counter. Finally i wants the simulation waveforms. I am counfused about what is input given so that output waveform generates. Please please help me, i am beginner in this subject

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity counter_fsm is
	 port(
		 updown : in STD_LOGIC;
		 clock : in STD_LOGIC;
		 lsb : out STD_LOGIC;
		 msb : out STD_LOGIC
	     );
end counter_fsm;
architecture counter_fsm of counter_fsm is
type count_state is (zero, one, two, three);
signal present_state, next_state	   : count_state;
attribute syn_encoding				  : string;
	attribute syn_encoding of count_state : type is "11 01 10 00";
begin  
	process (present_state, updown)
	begin
		case present_state is
			when zero =>
				if (updown = '0') then
					next_state <= one;
					lsb <= '0';
					msb <= '0';
				else
					next_state <= three;
					lsb <= '1';
					msb <= '1';
				end if;
			when one =>
				if (updown = '0') then
					next_state <= two;
					lsb <= '1';
					msb <= '0';
				else
					next_state <= zero;
					lsb <= '0';
					msb <= '0';
				end if;
			when two =>
				if (updown = '0') then
					next_state <= three;
					lsb <= '0';
					msb <= '1';
				else
					next_state <= one;
					lsb <= '1';
					msb <= '0';
				end if;
			when three =>
				if (updown = '0') then
					next_state <= zero;
					lsb <= '1';
					msb <= '1';
				else
					next_state <= two;
					lsb <= '0';
					msb <= '1';
				end if;
		end case;
	end process;
	process
	begin
		wait until rising_edge(clock);
		present_state <= next_state;
	end process;

	 -- enter your statements here --

end counter_fsm;


---------- Post added at 20:51 ---------- Previous post was at 20:37 ----------

Sir I have also tried the code provided by you also. The compilation shows no error. But i have confused about what is the input given so that the proper simulation waveform generates.

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity mealy_4s is

	port
	(
		clk		 : in	std_logic;
		data_in	 : in	std_logic;
		reset	 : in	std_logic;
		data_out : out	std_logic_vector(1 downto 0)
	);
	
end entity;

architecture rtl of mealy_4s is
type state_type is (s0, s1, s2, s3);
signal state : state_type;

begin
	process (clk, reset)
	begin
		if reset = '1' then
			state <= s0;
		elsif (rising_edge(clk)) then
case state is
				when s0=>
					if data_in = '1' then
						state <= s1;
					else
						state <= s0;
					end if;
				when s1=>
					if data_in = '1' then
						state <= s2;
					else
						state <= s1;
					end if;
				when s2=>
					if data_in = '1' then
						state <= s3;
					else
						state <= s2;
					end if;
				when s3=>
					if data_in = '1' then
						state <= s3;
					else
						state <= s1;
					end if;
			end case;
			
		end if;
	end process;
process (state, data_in)
	begin
		case state is
			when s0=>
				if data_in = '1' then
					data_out <= "00";
				else
					data_out <= "01";
				end if;
			when s1=>
				if data_in = '1' then
					data_out <= "01";
				else
					data_out <= "11";
				end if;
			when s2=>
				if data_in = '1' then
					data_out <= "10";
				else
					data_out <= "10";
				end if;
			when s3=>
				if data_in = '1' then
					data_out <= "11";
				else
					data_out <= "10";
				end if;
		end case;
	end process;
	
end rtl;
 
Last edited by a moderator:
  • Like
Reactions: imnimn

    imnimn

    imnimn

    Points: 2
    Helpful Answer Positive Rating
Your code works fine, you only need a testbench, do you know how to write one?
I have made it for you but you still need to add the clock and updown input signal.

Alex
 

Attachments

  • counter_fsm.zip
    804 bytes · Views: 170
sir what is problem in second program as and what are input parameter for both i am confused about that
library ieee;
use ieee.std_logic_1164.all;

entity mealy_4s is

port
(
clk : in std_logic;
data_in : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(1 downto 0)
);

end entity;

architecture rtl of mealy_4s is
type state_type is (s0, s1, s2, s3);
signal state : state_type;

begin
process (clk, reset)
begin
if reset = '1' then
state <= s0;
elsif (rising_edge(clk)) then
case state is
when s0=>
if data_in = '1' then
state <= s1;
else
state <= s0;
end if;
when s1=>
if data_in = '1' then
state <= s2;
else
state <= s1;
end if;
when s2=>
if data_in = '1' then
state <= s3;
else
state <= s2;
end if;
when s3=>
if data_in = '1' then
state <= s3;
else
state <= s1;
end if;
end case;

end if;
end process;
process (state, data_in)
begin
case state is
when s0=>
if data_in = '1' then
data_out <= "00";
else
data_out <= "01";
end if;
when s1=>
if data_in = '1' then
data_out <= "01";
else
data_out <= "11";
end if;
when s2=>
if data_in = '1' then
data_out <= "10";
else
data_out <= "10";
end if;
when s3=>
if data_in = '1' then
data_out <= "11";
else
data_out <= "10";
end if;
end case;
end process;

end rtl;
 

You can either use the code i have attached before and change the names , or if you want to do it your way then you change the states in the first process and you show result in the second process.

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity mealy_4s is

port (	clk : in std_logic;
		data_in : in std_logic;
		reset : in std_logic;
		data_out : out std_logic_vector(1 downto 0)
		);

end entity;

architecture rtl of mealy_4s is
	type state_type is (s0, s1, s2, s3);
	signal state : state_type;

begin
	process (clk, reset,DATA_IN)
	begin
	
	if reset = '1' then
		state <= s0;
	
	elsif (rising_edge(clk)) then
		case state is
		
			when s0=>
				if data_in = '1' then
					state <= s1;
				else
					state <= s0;
				end if;
			
			when s1=>
				if data_in = '1' then
					state <= s2;
				else
					state <= s1;
				end if;
				
			when s2=>
				if data_in = '1' then
					state <= s3;
				else
					state <= s2;
			end if;
			
			when s3=>
				if data_in = '1' then
					state <= s3;
				else
					state <= s1;
				end if;
		end case;
	end if;
end process;

process (state)
begin
	case state is
		when s0 => data_out <= "00";
		when s1 => data_out <= "01";
		when s2 => data_out <= "10";
		when s3 => data_out <= "11";		
	end case;
end process;

end rtl;

Alex

---------- Post added at 18:40 ---------- Previous post was at 18:34 ----------

You should also try to use meaningful names, when an input controls the counter direction, updown or direction is a better name to make the code easier to read.
You should also indent your code , see my code above how much easier it is to read.

Alex
 
hello this is my vhdl code for a 2bit counter
Code: 
library ieee;
use ieee.std_logic_1164.all;
entity two_bit_counter_FSM is
  port(clk,reset,load:in std_logic;count:out std_logic_vector(1 downto 0));
  end two_bit_counter_FSM;
  architecture arc of two_bit_counter_FSM is
    type state is (s0,s1,s2,s3);
      signal ps,ns:state;
      begin
      process(clk,reset)
        begin
        if(reset='1') then
          ps<=s0;
        elsif(clk'event and clk='1')then
        ps<=ns;
      end if;
    end process;
    
    process(ps,load)
      begin
        if(clk'event and clk='1')then
        case(ps)is
      when s0 =>
        if (load='1') then ns <=s1; else ns<=s0;
        end if;
      when s1 =>
        if (load='1') then ns <=s2; else ns<=s0;
        end if;
      when s2 =>
        if (load='1') then ns <=s3; else ns<=s1;
        end if;
      when s3 =>
        if (load='1') then ns <=s0; else ns<=s2;
        end if;
      end case;
      end if;
    end process;
    
    process(ps,load)
      begin
        if(clk'event and clk='1')then
        case(ps)is
      when s0 =>
        if (load='1') then count <="01"; else count<="00";
        end if;
      when s1 =>
        if (load='1') then count <="10"; else count<="01";
        end if;
      when s2 =>
        if (load='1') then count <="11"; else count<="10";
        end if;
      when s3 =>
        if (load='1') then count <="00"; else count<="10";
        end if;
      end case;
      end if;
    end process;
    
  end arc;

can someone help me to write a testbench and tell me what has to be done in a test bench
 
Last edited by a moderator:

in a testbench you would generate the clock and input signals for the unit under test, and then check that the output is correct.

Because you are not going to synthesise it, you can use non-synthesisable constructs like:

clock <= not clock after 10 ns; --50 MHz clock
load <= '1', '0' after 20 ns, '1' after 500 ns;

etc.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top