op amp two stage stability

Hello

I'm trying to quickly simulate the circuit in the figure

I tried other kinds of feedback networks but still get stability problems (output goes to rails)

Doing Monte carlo analysis with just 2% variation in the Vthreshold gives me a closed loop gain of around -50dB for more than 50% of the samples

Any input really appreciated
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Oops it didnt upload to edaboard I linked it from photobucket

Hi there,
For typical two-stage op amp miller compensation, R2 and C1 should be between the output of the first stage to the output of the second stage. It looks as though R2 has been chosen to be quite high to push the right half plane zero well into the left half plane which will not only boost the phase but increase the gain at lower frequencies. If tying the compensation resistor and capacitor to the output of the first stage doesn't work, try reducing the value of R2 to approximately equalize 1/gm of the PMOS at the output.

Additionally, for differential signals, R3 approximately does nothing since it will be tied between a virtual ground and ground, so I'm not sure what it's being used for. Also, the differential to single ended conversion at the second stage as opposed to the first stage with an active current mirror is atypical as well. This may also be causing stability problems due to the zero from the gate to drain capacitance from M5. I'll have to consider that stage in more detail.
Best.

Thanks for the reply
I tried changing the single ended output into the first stage and adding the miller compensation
The nominal closed loop gain is 55V/V but as we can see in the schematic, montecarlo varying threshold voltage for the transistors by just 5% throws the gain to 0 for most of the samples

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It looks like the inputs to the op amp are in phase (both have a .5 V ac) varying together so you could be looking at the common mode AC gain with the analysis?

Unless the slight mismatch, which would be amplified by the differential circuit, is amplified enough to rail the op amp (not sure if this is taken into account in this analysis).

Alternatively, you could try putting the amplifier into a unity feedback configuration and determine the error from a gain of 1. This may narrow down the number of problems that could be a result of looking at the op amp in an open circuit configuration.

Hope something in this ramble helps!

Thanks

I tried the unity feedback and still goes to the rails

I did the same with a simple common source amplifier with a diode load
The open loop gain was going to the rail with the 5% Vthreshold variation which is expected, but with the feedback network the closed loop gain varied by less than 1 % while doing monte carlo varying the VDD, Vthreshold and lambda by 5%

I guess I need to read more into differential amplifier feedback
Probably the 5% threshold variation is throwing some of the transistors out of saturation

Do simulation, you use voltage source to bias MOS　Ｍ７　that maybe lead the output pull high or pull low (without gain) when you do montecarlo. M7 should a current source relate to I1.
For a Amp the M1 M2 need large Gm but M3 M4 need large Rds so the size of M3 and M4 should be small.

In your circuit, the C1 is too large that can not integrated in chip.
For so large value 50U, R5 is 0, maybe your circuit is stabe.
For the 2 stage AMP you shoule analyse where is first pole, where is second, how much loading. If you loading is very large cap, you don't need miller compensation at that time the miller maybe is not good for stable.
If you want to learn how to design AMP:
First you should analysis the amp, not to do simulation.
Calculate the pole and zero first.

And you should know what the gain, bandwidth etc you needed. from that get the tail current value.
Then give a current source as bias (example use the current source replace R1 in your first ciruit)
Then make the M9 and M10 is saturation (give a 0.2 Vod).
The M1 M2 can in stauration or cutoff region (need larger size). the M3 and M4 need larger Rds (small size).
The miller compsenation must relate to output loading.

Thanks for the help

I was able to get less than 1v deviation in montecarlo for closed loop gain of 30V with circuit in figure below

I have some more questions

-- To bias the input stage for a CM voltage of ground I had to add those two 11k resistors, is there a better way to do this?
-- Is there somewhere with guidelines for IC design, like good size limits for capacitors resistors etc
-- I connected the bulk for the input to gnd and for the current mirror nmos to -3.3 rail, is this how it should be done?
-- For the Ibias would it be implemented with a resistor in the deisgn?

Still waiting on my analog book to arrive, just trying to find info online

All the help appreciated

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You should read some book first.
The Razavi's "Design of Analog CMOS Integrated Circuits" is a good basic tech. book.

Your circuit's DC value is wrong.(M3/M4 ration error)
first set a right dc value in your circuit.
R1 R2 is not useful in AMP.
IBIAS need design bias generation circuit. Detail please reference book.