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PMOS and NMOS should be isolated to avoid latch up.
Surround the NMOS with NWELL ring and surround the PMOS with P+ ring.
( you can use deep nwell also to isolate if your process supports that)
Refer to Technology manual for this. If you run DRC you should see fails related to latchup if your design does not meet the latch criteria. (or) read the tech manual before trying to design layout.
I am assuming here you are getting Latchup Related DRC Errors for your Layout.
These rules are coded to ensure your design should not result in failure because of CMOS Latch up Problem after fabrication.
To overcome these errors in your layout, you need to go for Latchup Prevention techniques.
There are many prevention techniques for Latchup. Go through your design, layout and find out which will best suit to make your layout DRC clean as well as effective.
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