zhipeng
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Say, in the top level verilog netlist, it instantiates four instances of the same module DECODER.
After RTLCompiler has done elaborate and synthesis, they becomes instances of four differently-named modules, DECODER, DECODER_1667, DECODER_1668, and DECODER_1669.
How do I prevent the same module been renamed and re-synthesized to different implementations?
Later in hierarchical P&R, if I make one of the four copies as master partition, what is the command to make the other three into clones of the master partition?
After RTLCompiler has done elaborate and synthesis, they becomes instances of four differently-named modules, DECODER, DECODER_1667, DECODER_1668, and DECODER_1669.
How do I prevent the same module been renamed and re-synthesized to different implementations?
Later in hierarchical P&R, if I make one of the four copies as master partition, what is the command to make the other three into clones of the master partition?