Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to clear DRC violations

Status
Not open for further replies.

chanducs24

Member level 2
Member level 2
Joined
Oct 20, 2010
Messages
53
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,598
hi

i got huge drc violations after i ran drc..can anyone suggest how to clear these?

Thanks,
chandra.
 

Hi,

What types of errors are you getting?

What is the frequency of the various errors? (how many of each type)
 

Follow the DRC Rules! Look at the documentation for your technology.

Other tips:

Do DRC various times while making the layout. That way you won't be overwhelmed in the end.

Always instantiate smaller blocks like basic gates. If you first build a library with basic cells like NANDS, NORS, etc, and make sure these are DRC and LVS clean, you can use them freely in other layouts by instantiating them. On the other hand, imagine copy pasting the layout for an inverter 10 times. Even a single mistake will now appear 10 times.
 

Hi Chandra,

If you get thousands of Errors the problem may be one or more of below points;

1 - Floorplan objects (power straps, missing tap fillers, overlapping cells, etc...)
2 - Latch-up Errors that may be caused by missing tap cells
3 - Density errors as I guess you have not do metal filling.
4 - Or any other problem that originates from a repeated structure...

Below are general guidelines for DRC fixing;

1 - Normally before starting placement step and after floorplanning step, you should check your floorplan and clean floorplan related DRC violations. If you don't clean them at this stage it will be very hard to clean after post route.

2 - After floorplan, doing a quick & dirty placement and checking for latch-up errors should save a lot of time later at post-route step.

3 - After post route, you should clean all DRCs in Place and Route tool and then check with Signoff DRC tool to prevent time consuming DRC closure loops.

4 - After finishing DRCs seen by Place and Root tool, export the design and run DRC check with Calibre (or any other drc checker). Then fix remaining DRCs manually.

Important: If you see huge number of DRC violations, the problem may be very simple to fix, bur you may need to re-visit floorplan stage depending on the DRC violation.

I hope above points help,
BR,
Gokhan
---
 
Last edited:
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top