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[SOLVED] CMOS Antenna Ratio Rules

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Radike

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Hi,
I am in the process of designing a CMOS RFic. I am getting an antenna ratio rule error related to gate poly area.

Once solution is to use a diode to fix this problem. However, I am not sure what is the size of the diode, number of diodes and where exactly I need to place the diodes. Can somebody help me regarding this?

Thanks a lot!!!
 

Radike said:
I am not sure what is the size of the diode, number of diodes and where exactly I need to place the diodes. Can somebody help me regarding this?
Click to expand...

The tinyest diode is enough, and only 1 (one) of them. Put it directly (anywhere) under the M1 connection of the resp. node, either n+ in p-substrate or p+ in n-well (n-well connected to VDD). Personally I think the latter one is safer, as it protects with just one diode forward drop against positive charges being injected during ion etch (in the very last seconds of the etch process, when the individual metal connections are separated from each other).

An n+ on p diode would have to go in reverse breakdown (by positive charge), and this voltage could be too high for a gate.

Positive charges from (several) ion etch processes are the most dangerous potential damage causes for antenna problems. Of course there's also a possibility of negative charge deposition during the drying process (by friction) after each CMP process step - with lower probability for damaging, however.

If you want to be on the safe side, put both diodes per antenna threat. (I never did - always used only p+/n-well diodes - successfully ;-) ).

BTW: Your question - IMHO - would better fit into the Analog IC Design & Layout forum.
 
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To Radike,
Antenna check is layer by layer.
Which layer did you get this error? - if poly, then perhaps it might be the case, you are using too much poly for interconnect between the MOS gates.
Use Jumper rule first to avoid as much as you can.
I won't recommend using reverse-bias diodes as a first method, diode insertion is bad w.r.t. low-power, because of junction leakage and it inadvertently it introduces additional depletion capacitance in the associated net, which again is a variable cap depends on state of the signal 0/1 and choice of diode.

Inserting a diode changes the antenna equation - usually the ratio-relaxation obtained is orders of magnitude higher, however that essentially means, diode area matters. Check the foundry DRM [design rule manual] - or the Antenna rules file. Hence I won't agree to erikl, that a tiniest diode will solve all antenna.

Well, if you choose to place a diode.
First check antenna math, e.g. solution, that you have to use diode of area "A".


- I appreciate your concern - should I use 1*A or, 2 diodes of area A/2 each, or a 4 * A/4?
in addition the interesting question you asked - where to place the diode.
I'd say apply and physics and common-sense.
This breakdown mechanism is TDDB failure - use common sense to see charge collection topology and place relatively in the middle. Or distribute diodes in such a way that leads to optimal charge leak path. Collected charges/ions anywhere would traverse similar min path length, from anywhere on conductor coordinate to nearest diode. Another approach could be to balance/optimize the placement you got from above - with the thought that eventually you are going to save the GATEs so distance from any gate to nearest diode is balanced.
 
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sat said:
To Radike,
Antenna check is layer by layer.
Which layer did you get this error? - if poly, then perhaps it might be the case, you are using too much poly for interconnect between the MOS gates.
Use Jumper rule first to avoid as much as you can.

Hi,
Thanks for the quick response. At the moment I am getting two types of errors.
First: cumulative metal area (M1 to Top Metal) to the related gate Poly2 area on thin gate devices
Second: Maximum ratio of Metal Top area to the related gate Poly2 area on thin gate devices.

I tried using jumpers. But I have 5 inductors connecting to my three transistors. Inductor uses thick metal top and big in size compared with Poly2 area on thin gate devices. So I think I need to use diodes.
I can pass the DRC even if I use the smallest diode. But can I trust DRC regarding this?

---------- Post added at 05:41 ---------- Previous post was at 04:39 ----------
erikl said:
The tinyest diode is enough, and only 1 (one) of them. Put it directly (anywhere) under the M1 connection of the resp. node, either n+ in p-substrate or p+ in n-well (n-well connected to VDD). Personally I think the latter one is safer, as it protects with just one diode forward drop against positive charges being injected during ion etch (in the very last seconds of the etch process, when the individual metal connections are separated from each other).

Hi,
Thanks for the quick reply. My circuit is similar to a Distributed amplifier topology. The errors are related to (Metal1 to MetalTop to the related gate poly2 on thin gate devices and MetalTop area to the related Poly2 area on thin gate devices). Is it possible to know what you meant by the resp. node?

Thanks alot!!!
Click to expand...
Click to expand...
 

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