jhasan
Newbie level 4
I am designing a simple two input nor gate.
But I get an LVS error.It seems that the nmos which are parallel are not merging.
In the LVS error report I get:
=================================================
=========Matched Instances with Bad Net Connections======
=================================================
Schematic Instance: MN2 enm
Layout Instance: avD62_1 n
Pin SchNet LayNet
---- ------- -------
S gnd! Out
D Out gnd!
Looking at this it seems the parallel mosfets in th pulldown network of NOR gate are not merging.Is there a way I can solve this problem?Any help would be greatly appreciated.
But I get an LVS error.It seems that the nmos which are parallel are not merging.
In the LVS error report I get:
=================================================
=========Matched Instances with Bad Net Connections======
=================================================
Schematic Instance: MN2 enm
Layout Instance: avD62_1 n
Pin SchNet LayNet
---- ------- -------
S gnd! Out
D Out gnd!
Looking at this it seems the parallel mosfets in th pulldown network of NOR gate are not merging.Is there a way I can solve this problem?Any help would be greatly appreciated.