shshprsd
Junior Member level 3

I am using a spartan 3A dsp board clock to the board is 100Mhz but the manual says all differential i/o are working more than 662 Mhz, how it can be?
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That's correct, if the data is latched at one edge only. The high speed output on FPGA like Spartan 3A is provided by DDR (double data rate) registers, multiplexing two data lines to one output pin. So it can generate 500 MS/s with 250 MHz core clock. But I fear, the DAC needs a true 500 MHz clock, that can't be generated by Spartan 3A.A 500 MSPS data will have a bit period of 1/500 e6 = 2 ns .
If data is latched at +ve edge of clock than clock should have 1 ns of on period and 1 ns of off period ok immaterial of duty cycle it should complete one cycle in 2 ns since time period of clock is 2 ns so clock frequency comes to be 1/2ns = 500 Mhz.