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Reading OUT ports for debugging

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Richard29

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Hi,

I have a FIFO which has an interface that looks something like this:

Code: 
entity fifo is
    port (
    CLK                       : IN  std_logic := '0';
    DIN                       : IN  std_logic_vector(31 DOWNTO 0);
    ALMOST_EMPTY      : OUT std_logic;
    ALMOST_FULL         : OUT std_logic;
    DOUT                    : OUT std_logic_vector(31 DOWNTO 0);
    EMPTY                   : OUT std_logic;
    FULL                     : OUT std_logic;
    OVERFLOW             : OUT std_logic;
    WR_ACK                 : OUT std_logic
);
end fifo;

This interface is given and I can't change is. The thing is now, for debugging purposes, I wanna see what is written and read to/from the FIFO. In other words, ideally I would like to assign two debug the in and out values of the FIFO, ie.

Code: 
      DBG_FIFO_IN    <= DIN;
      DBG_FIFO_OUT <= DOUT;

For obvious reasons, the second assignment gives me the following error message:

[exec] ERROR:HDLParsers:1401 - Object DOUT of mode OUT can not be read.

So I am wondering if there is any way how I can assing the DOUT value to my debug symbol. The interface is given, so I cant make DOUT an inout signal.

Many thanks for helpful comments!
 

where do you add these assignement?
Inside the architecture of FIFO?

Regards,
Jerome
 

No Jerome, It is in another Module where I have an instance of the FIFO and from there I wanna read somehow the
output from the FIFO. As stated earlier, the interface of the FIFO is given, I cannot change here anything.
 

Yes, and at some point I end up at the top level signal with the debug signal where I assign it then to the Chipscope ILA core for debugging purposes
 

then the problem is simple.
you must use intermediate signals like this

fifo1 :fifo(...,DOUT=>dout_int;....);
DBG_FIFO_OUT <= dout_int;
DOUT<=dout_int;
In vhdl the only way you can use an output port is at left hand of an assignement.

Regards,
Jerome
 
Oh yes, it is indeed easy ;) Thanks a lot!
 

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