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binary to ASCII converter in VHDL needed

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oliverlin09

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ASCII converter

Hi all,

I am wondering where I could find some information about binary to ASCII converter in VHDL???
 

There is not such thing as ASCII in VHDL, what do you want to do? Implement printf?
 
My FPGA will get some data, and I would like to transfer those data from binary to ASCII before I send them to a PC.
 
Ok, once again it is not clear, what do you mean by converting to ASCII, ASCII is binary data. o you want to convert integer values to ASCII value of it or something similar? Are you trying to connect your FPGA to a computer terminal?

Your question doesn't make sense if you don't clarify it more.
 

Sorry about that.

I use FPGA (Spartan-3) to connect to a PC via USB port.
I would like to transfer binary values to ASCII values, because computers can read ASCII.
And then I can use software to read or analyse those ASCII values.
I don't know if it's clear.
 

This is really getting nowhere. Do you know ANYTHING about USB or FPGA at all?

First of all, Using USB to communicate between an FPGA and a PC is like trying to fly a 747 in order to go to your friends home next door.

USB is complicated, difficult and complex protocol and in NO WAY it is communicating in ASCII, unless you have a special device/program that does this for you.

If you use a serial port, then you can use a simple terminal program on the PC and a simple rs232 IP on the FPGA to make the communication, then you can write a simple code to convert your binary data to HEX values in ASCII, this should be simple enough to do.
 

I use Spartan-3, and the chip controls USB port is CP2101.
Actually, it uses serial port's concept to do communication.
Using it, I will need to install CP2101's driver, then connect with a PC and it will be shown as a virtual COM port.
So in this case, I just need to build a RS232 UART, and I can connect the FPGA with a PC via USB port.
 

Yes, that is the case, but you need to write a controller to manage the data communication via RS232 on your FPGA.
 

Hello. I have similar problem. I need to send data from FPGA to PC.

For example..
I have:
std_logic_vector (7 downto0) = 11100011; -- represent value 153

I need to send 1 (49) , 5 (53) and 3 (51) because RS232 is ASCII coded!

Can someone help me how to convert std_logic_vector TO ASCII values.
code can be in VHDL or Verilog.

Thanks a lot.
 

As posted before, ASCII is binary. There is no conversion at all. A std logic vector is just a collection of bits. The data inside the std_logic_vector could be an integer, it could be ascii, it could be BCD, it could be whatever you want it to be. Its just a collection of bits.

Is this data not already ascii? what encoding scheme does it use?
 
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OK. I will refraze my question.

I need function in vhdl or Verilog vith:
RegisterIN : IN std_logic_vector (7 downto0);
Numb1 : OUT std_logic_vector(3 downto 0);
Numb2 : OUT std_logic_vector(3 downto 0);
Numb3 : OUT std_logic_vector(3 downto 0);

IF RegisterIN is 10011001 --153 in Dec,

Numb1 must be 0001 -as 1 in dec
Numb2 must be 0101 -as 5 in dec
Numb3 must be 0011 -as 3 in dec

This is IT !!!!
 

You're going to need a divider to work out all of the different base 10 values you need. These are expensive bits of hardware.Then using that it should be straight forward to extract 1, 5 and 3.
 
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Yes, you are right.

I am looking for the alternative solution if it exists. But i think I will solve this problem on PC. I will just send RegisterIN as it is and decode it in VB.

Thanks anyway :)
 
if you want to send ASCII in binary form you had to convert first the binary.. by detecting your binary no. like either it is a integer (0 to 9) or alphabet (A to Z) or (a to z) and then adding accordingly 30(hex) (0011 0000) for 0 to 9 of your detected binary then 41(hex) for A to Z and rest all like that.

but first you had break the incoming data bits, analyze them, process them, and then concatenate.. i hope this helps you..!!
 
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basically, it sounds like they are asking for a VHDL itoa block. The conversion is easiest on the PC side, as you've mentioned. raw binary is undecipherable with standard terminal programs. hexadecimal can be useful for numeric data that needs to be printed by a standard terminal, and base64 works for arbitrary data that needs to be printed by a standard terminal. If you don't ever need to look at the data using a standard terminal, then binary is a good choice, as it is link efficient.
 
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Thanks a lot. I have allready done it in visual basic.

But if anyone know another way, how to break bits apart let me know. Devide with 10 and save number as integer is not a good idea for FPGA, it require to many recorses as TrickyDicky said.
 

Hi. The easiest way to do "byte" to "bcd expansion" is a simple case statement with all 255 options explicitlyy defined. The operation is then a basic boolean 8-bit lut function per each output bit

NOTE: you will need to specify a "no rom extract" synthesis attribute to stop quartus or xst inferring a ROM block.

the following will reduce to a 31 LUT implementation in the FPGA a V5,S6,V6,Arria or Stratix etc....

e.g.
case (in_byte) is
when x"00" => val <= X"000";
...
when x"FE" => val <= X"254";
when others => val <= X"255";

voila, nice compact expander. :wink:
 
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ZigaM said:
OK. I will refraze my question.

I need function in vhdl or Verilog vith:
RegisterIN : IN std_logic_vector (7 downto0);
Numb1 : OUT std_logic_vector(3 downto 0);
Numb2 : OUT std_logic_vector(3 downto 0);
Numb3 : OUT std_logic_vector(3 downto 0);

IF RegisterIN is 10011001 --153 in Dec,

Numb1 must be 0001 -as 1 in dec
Numb2 must be 0101 -as 5 in dec
Numb3 must be 0011 -as 3 in dec

This is IT !!!!
Click to expand...



I have done something similar in a function for avr to convert a long unsigned integer to a string.
You make subtractions instead of division,

you make a loop to subtract 100 from the input number and after each subtraction you increase the first digit of the output by 1 until the number is lower than 100
then you do the same using 10 (increasing the second output digit) and 1 (increasing the third output digit) until the number is 0.

234 - 100 output 100 (Numb1=1, Numb2=0, Numb3=0)
134 - 100 output 200
034 is lower than 100

034 - 10 output 210
024 - 10 output 220
014 - 10 output 230
004 is lower than 10

004 - 1 output 231
003 - 1 output 232
002 - 1 output 233
001 - 1 output 234 (Numb1=2, Numb2=3, Numb3=4)
000 stop

i don't know if this takes many resources in VHDL because i haven't tried it but is can be done.

Alex
 
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I found another article,it is the same method but it is easier to understand and has nice examples

Binary to BCD Converter
and pdf version **broken link removed**

Alex
 

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