Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
do you have any literature, i am trying to implement it in cadence. the whole adc should drive a 50ohm resistor where should the 50 ohm resistor connected
I don't think the ADC should drive a 50ohm resistor. Maybe, you mean that the ADC should have a 50ohm input termination...
Just do a search on the IEEExplore website or google for "pipeline ADC" and you will find tons of references.
1- Regarding your digital, you need to design the clock generator circuit (non-overlapping clock), digital correction logic and the MDAC ( comparator + some gates + ...)
2- About literature, you can find theory in the following thesis (available in google):
(a) Design for Reliability of Low-voltage, Switched-capacitor Circuits by
Andrew Masami Abo
(b) A POWER OPTIMIZED PIPELINED ANALOG-TO-DIGITAL CONVERTER DESIGN IN DEEP SUB-MICRON CMOS TECHNOLOGY - Chang-Hyuk Cho
(c) A 10-bit 25Msps Pipeline ADC for Companding Baseband Processing in Wireless Application - Shenjie Wang
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
