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How to convert 10M sinwave to square wave with phase noise better than -135dBc/Hz@1K

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tony_lth

tony_lth

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I have a 10M sinwave signal, and I want it to be divided-by-4 with HMC365. for sinwave, the minimum input freq is 200M, but for square wave, the HMC365 can operate to DC. So I have to convert 10M sinwave to square wave.

The 10M sinwave phase noise is -140dBc/Hz@1KHz, and HMC365 noise floor is -135dBc/Hz@1KHz. HMC365 use flip-flop tech, frankly I don't know it at all.
So I need one IC convert 10M sinwave to square wave, make it divided-by-4 with HMC365, then convert 2.5M square wave to sinwave, the 2.5M sinwave should have phase noise better than -135dBc/Hz@1KHz.

Anyone can recommend the IC for me?:???:

HMC365 use InGaP GaAs HBT technology, so I guess the IC using this tech should meet the PN requirement.
 

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You could maybe do it all with just a Peregrine PE3512 and don't bother with the Hittite part.

**broken link removed**

I don't know what noise performance the PE3512 has (it is a dual flip flop circuit inside) but it will probably do what you want. It's worth getting one to measure it or you could ask Peregrine for advice about the noise performance.

At 10MHz, there's probably cheaper ways to do what you want by using a basic 74HC74 dual flip flop with a squarer ahead of it (eg unbuffered CMOS inverter biased into the linear region might meet the noise requirements)

But I would have to check out the noise on an analyser first eg I'd use an Agilent E5052A to measure the noise performance of either circuit in a few seconds.

There's also a low noise squarer circuit somewhere in the classic Rohde PLL book and I think it uses a pair of PNP transistors. I did use this circuit may years ago but I don't know how good it really is as I didn't have access to anything like an E5052 back then.

edit:
Just remembered that the E5052 only works down to 10MHz so I'd have to do something like mix the 2.5MHz with a low noise 10MHz source to get the 5052 to see it at 12.5MHz.
 
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I think you should BiPolar technology because 1kHz is around flicker noise corner and CMOS circuits have higher flicker noises than bipolars.
 
Using a CMOS gate as level converter most likely doesn't keep the phase noise specification. Apart from converting CMOS flicker noise into phase noise, as mentioned, it's also sensitive to supply voltage interferences. You should use a good standard comparator with sufficient speed. Unfortunately, manufacturers rarely specify jitter performance data of comparators, except for very high speed types.
 
I would never have considered using a comparator here.

The unbuffered gate might not be as bad as you think. The spec is -135dBc/Hz at 1kHz.

Sure, a discretely designed differential amp (squarer) using NPN or PNP transistors followed by a 74LS74 will probably give the lowest noise at the divided output (it would probably reduce the phase noise at the 2.5MHz output closer to -152dBc/Hz, i.e. could be up to 12dB lower than the -140dBc/Hz at the 10MHz source due to the divide by 4) but I would have thought the unbuffered gate feeding a 74HC74 would still meet the -135dBc/Hz spec (but I'm only guessing here so I'd measure it to make sure)
 
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I would never have considered using a comparator here.
Click to expand...
But why? It's properties aren't much different from a discrete circuit.

P.S.: I rembered, that a similar topic has been discussed before. A user provided an interesting link to an atomic clock user manual with suggestions for a 10 MHz sine to square conversion circuit, including phase noise measurements. According to the data, a CMOS gate converter achieved < -150 dB @ 1kHz.
https://www.edaboard.com/threads/130847/
 
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I wouldn't choose a comparator because I am unfamiliar with using them for this type of application. I would have assumed that they would generate much higher phase noise. Also, they would cost more.

For me the first solution I would investigate for the -135dBc/Hz spec would be the cheapo CMOS solution. If I was after ultimate phase noise then maybe look at a discrete design feeding a 74LS74 or maybe a different 74 family (i.e. try different families). But the spec doesn't call for this level of performance so it would perhaps be unnecessary and would cost more and take more space :)
 
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The said publication suggests that your doubts regarding comparator phase noise are at least justified with the LT1016 used in the comparison.
 
Maybe you should try some logic families and post the phase noise results. Logic families come and go on a monthly basis! Hard to keep track.
 
biff44 said:
Maybe you should try some logic families and post the phase noise results. Logic families come and go on a monthly basis! Hard to keep track.
Click to expand...
OK, I will try to use XILINK XC3 FPGA to do the test and will post the results here, but it will take several days.
 

The jitter introduced by a FPGA must be expected to increase the clock phase noise considerably.

How do you want to measure the phase noise?
 
I want to use Agilent E5052A signal analyser directly test the FPGA output TTL signal. The TTL output is high impedance, but E5052A is 50R, I guess the signal level will be pulled down and I expect that signal level should be more than -10dBm and if so don't influence the test result. I think the fundamental tone occupied major power, and it will take about one month to make the LPF filters, so I will test the TTL output directly.
 

A TTL output is not actually high impedance. It should be fine to place a 50 ohm series resistor and a capacitor at the output and connect it directly to a 50 ohm cable.
 
I still think that the weak link is the oscillator and not the squarer and divider.
A simple discrete squarer based on a differential amplifier driving a pair of TTL flip flops to do the divide by 4 will be capable of sub -160dBc/Hz at 1kHz offset (but the source oscillator phase noise will limit this).

This is (ultra low cost) 35 year old technology and will easily meet the spec of -135dBc/Hz. It will probably exceed the measurement capability of the E5052A and it costs less than $1. I don't understand why modern 11GHz prescalers or comparators or Xilinx FPGA are being considered.
 
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I dug out an old copy of Manassewitsch and this shows a plot supplied by HP showing the divider noise of TTL with a low noise 20MHz clock being divided to 2MHz and the noise is well below -160dBc/Hz at a 1kHz offset.

Click on the link below to see a circuit that I used several years ago to provide a low noise squaring circuit at 10MHz. I'd like to think this will give good performance but it was never measured directly although it was used for a reference for a low noise synthesiser running at 2.5GHz. I don't recall having issues with high phase noise at a 1kHz offset despite the x250 (48dB) multiplication of the reference noise.

View attachment squarer.doc
 
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biff44 said:
Maybe you should try some logic families and post the phase noise results. Logic families come and go on a monthly basis! Hard to keep track.
Click to expand...
I used FPGA XC3S500E do the freq divider, the results is as following:
Input: 120M, -151.9dBc/Hz@1KHz, -152.9dBc/Hz@10KHz
divide-by-10: 12M, -118.3dBc/Hz@1KHz, -122.2dBc/Hz@10KHz (Tested by E5052A signal source analyser)
divide-by-128: -115dbc/Hz@1Khz, -120dBc/Hz@10KHz. This is tested by spectrum analyzer.
Although I input 2M to the IF input port of E5052A front panel, but E5052A not tested auto. I failed to find any setting to test below 10M. Anyone can suggest?
 

Take a look to Wenzel ideas, who have a long experience developing low phase noise dividers/multipliers circuits.

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