Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Basic Layout question (inverter)

Status
Not open for further replies.
N

Nightlamp

Newbie level 4
Newbie level 4
Joined
Oct 19, 2010
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,340
Hello all! I have a really basic(well seems that way at least) question that I can just not figure out.

In one of my classes we are doing a simple lab to get familiar with a layout program where we create an inverter.

My question is this what exactly is the need for the P-substrate contact and N-substrate contact?

I have searched through the textbook and the internet and cannot seem to find an explanation for that.
 

Sure I cant post links yet so this is just a filler

---------- Post added at 21:27 ---------- Previous post was at 21:23 ----------

So I found this article on the internet **broken link removed** towards the bottom it talks about a "P-substrate contact" where a P-select region is attached to the NMOS transistor(and N-select next to the PMOS transistor). I just don't really understand what those are as I have never encountered them until this design.
 

I am not sure do you mean the bulk connection. If the answer is yes, for NMOS, put another active and P+ select and connect it to the Source of your NMOS together to the ground. The PMOS is opposit and connect to VDD (N+select inside N-well).
 
you just draw your PMOS and NMOS on schematics symbols and then transfer it to layout using stick diagram. =) It is the same.. XD

---------- Post added at 04:13 ---------- Previous post was at 04:08 ----------

Your NMOS gate will be conncted to your PMOS gate. Your Source of PMOS to +ve Power supply, Source of NMOS to GND. Both Drain of PMOS and NMOS is connected together. That's where your output will be also :)
 
As you know NMOS is formed on the P-substrate and PMOS is formed on NWELL. If there is no definite potential applied to substrate it can go to any potentail, the effects of this are,
1. If the substrate potential is more than source and drain then this can forward bias the junction making device to failure.
2. Change in the Vt of the device because of back bias effect.
 
Thanks all! This really helped me understand what the bulk connection actually does!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top